* [PATCH v3 0/2] riscv-imsic/aplic: Preserve IMSIC and APLIC states during suspend
@ 2025-12-02 6:07 Nick Hu
2025-12-02 6:07 ` [PATCH v3 1/2] irqchip/riscv-imsic: Add a CPU pm notifier to restore the IMSIC on exit Nick Hu
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Nick Hu @ 2025-12-02 6:07 UTC (permalink / raw)
To: Anup Patel, Thomas Gleixner, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti
Cc: linux-riscv, linux-kernel, Yong-Xuan Wang, Cyan Yang, Nutty Liu, Nick Hu
Since the APLIC and IMSIC may be reset when the platform enters a deep
sleep state, it is necessary to implement save and restore functions
to ensure their states are correctly preserved and restored.
Chagnes in V3:
- Refine the commit messages and comments
- Rename "imsic_restore()" to "imsic_hw_states_init()"
- Rename "aplic_direct_restore()" to "aplic_direct_restore_states()"
- Rename "aplic_add()" to "aplic_pm_add()"
- Rename "aplic_remove()" to "aplic_pm_remove()"
- Rename "aplic_save()" to "aplic_save_states()"
- Rename "aplic_restore()" to "aplic_restore_states()"
- Use "struct aplic_saved_regs" and "struct aplic_src_ctrl" to preserve
the APLIC states
Changes in V2:
- Address the compile error from kernel test robot when
CONFIG_RISCV_M_MODE is enabled.
- Rename "imsic_notifier_block" to "imsic_pm_notifier_block"
- Reanme "aplic_notifier" to "aplic_pm_notifier"
- Make aplic_add() as static and directly call it from aplic_setup_priv().
- Rename "list" as "head" and make it first variable in "struct aplic_priv"
Nick Hu (2):
irqchip/riscv-imsic: Restore the IMSIC registers
irqchip/riscv-aplic: Save and restore APLIC registers
drivers/irqchip/irq-riscv-aplic-direct.c | 11 ++
drivers/irqchip/irq-riscv-aplic-main.c | 158 ++++++++++++++++++++++-
drivers/irqchip/irq-riscv-aplic-main.h | 11 ++
drivers/irqchip/irq-riscv-imsic-early.c | 41 ++++--
4 files changed, 212 insertions(+), 9 deletions(-)
--
2.17.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
---
Nick Hu (2):
irqchip/riscv-imsic: Add a CPU pm notifier to restore the IMSIC on exit
irqchip/riscv-aplic: Preserve APLIC states across suspend/resume
drivers/irqchip/irq-riscv-aplic-direct.c | 10 ++
drivers/irqchip/irq-riscv-aplic-main.c | 166 ++++++++++++++++++++++++++++++-
drivers/irqchip/irq-riscv-aplic-main.h | 19 ++++
drivers/irqchip/irq-riscv-imsic-early.c | 39 ++++++--
4 files changed, 225 insertions(+), 9 deletions(-)
---
base-commit: 1b5dd29869b1e63f7e5c37d7552e2dcf22de3c26
change-id: 20251118-preserve-aplic-imsic-028bbb5d18da
Best regards,
--
Nick Hu <nick.hu@sifive.com>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 1/2] irqchip/riscv-imsic: Add a CPU pm notifier to restore the IMSIC on exit
2025-12-02 6:07 [PATCH v3 0/2] riscv-imsic/aplic: Preserve IMSIC and APLIC states during suspend Nick Hu
@ 2025-12-02 6:07 ` Nick Hu
2025-12-15 21:46 ` [tip: irq/drivers] " tip-bot2 for Nick Hu
2025-12-02 6:07 ` [PATCH v3 2/2] irqchip/riscv-aplic: Preserve APLIC states across suspend/resume Nick Hu
2026-02-20 4:10 ` [PATCH v3 0/2] riscv-imsic/aplic: Preserve IMSIC and APLIC states during suspend patchwork-bot+linux-riscv
2 siblings, 1 reply; 8+ messages in thread
From: Nick Hu @ 2025-12-02 6:07 UTC (permalink / raw)
To: Anup Patel, Thomas Gleixner, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti
Cc: linux-riscv, linux-kernel, Yong-Xuan Wang, Cyan Yang, Nutty Liu, Nick Hu
The IMSIC might be reset when the system enters a low power state, but on
exit nothing restores the registers, which prevents interrupt delivery.
Solve this by registering a CPU power management notifier, which restores
the IMSIC on exit.
Reviewed-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Cyan Yang <cyan.yang@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com>
Signed-off-by: Nick Hu <nick.hu@sifive.com>
---
drivers/irqchip/irq-riscv-imsic-early.c | 39 ++++++++++++++++++++++++++-------
1 file changed, 31 insertions(+), 8 deletions(-)
diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c
index 2c4c682627b8cc81ad51a98a1f341aa506d649ac..d1727c343c38f6f88a25b3327aaa080c1cfe3078 100644
--- a/drivers/irqchip/irq-riscv-imsic-early.c
+++ b/drivers/irqchip/irq-riscv-imsic-early.c
@@ -7,6 +7,7 @@
#define pr_fmt(fmt) "riscv-imsic: " fmt
#include <linux/acpi.h>
#include <linux/cpu.h>
+#include <linux/cpu_pm.h>
#include <linux/export.h>
#include <linux/interrupt.h>
#include <linux/init.h>
@@ -128,14 +129,8 @@ static void imsic_handle_irq(struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
-static int imsic_starting_cpu(unsigned int cpu)
+static void imsic_hw_states_init(void)
{
- /* Mark per-CPU IMSIC state as online */
- imsic_state_online();
-
- /* Enable per-CPU parent interrupt */
- enable_percpu_irq(imsic_parent_irq, irq_get_trigger_type(imsic_parent_irq));
-
/* Setup IPIs */
imsic_ipi_starting_cpu();
@@ -147,6 +142,18 @@ static int imsic_starting_cpu(unsigned int cpu)
/* Enable local interrupt delivery */
imsic_local_delivery(true);
+}
+
+static int imsic_starting_cpu(unsigned int cpu)
+{
+ /* Mark per-CPU IMSIC state as online */
+ imsic_state_online();
+
+ /* Enable per-CPU parent interrupt */
+ enable_percpu_irq(imsic_parent_irq, irq_get_trigger_type(imsic_parent_irq));
+
+ /* Initialize the IMSIC registers to enable the interrupt delivery */
+ imsic_hw_states_init();
return 0;
}
@@ -162,6 +169,22 @@ static int imsic_dying_cpu(unsigned int cpu)
return 0;
}
+static int imsic_pm_notifier(struct notifier_block *self, unsigned long cmd, void *v)
+{
+ switch (cmd) {
+ case CPU_PM_EXIT:
+ /* Initialize the IMSIC registers to enable the interrupt delivery */
+ imsic_hw_states_init();
+ break;
+ }
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block imsic_pm_notifier_block = {
+ .notifier_call = imsic_pm_notifier,
+};
+
static int __init imsic_early_probe(struct fwnode_handle *fwnode)
{
struct irq_domain *domain;
@@ -199,7 +222,7 @@ static int __init imsic_early_probe(struct fwnode_handle *fwnode)
cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_IMSIC_STARTING, "irqchip/riscv/imsic:starting",
imsic_starting_cpu, imsic_dying_cpu);
- return 0;
+ return cpu_pm_register_notifier(&imsic_pm_notifier_block);
}
static int __init imsic_early_dt_init(struct device_node *node, struct device_node *parent)
--
2.34.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 2/2] irqchip/riscv-aplic: Preserve APLIC states across suspend/resume
2025-12-02 6:07 [PATCH v3 0/2] riscv-imsic/aplic: Preserve IMSIC and APLIC states during suspend Nick Hu
2025-12-02 6:07 ` [PATCH v3 1/2] irqchip/riscv-imsic: Add a CPU pm notifier to restore the IMSIC on exit Nick Hu
@ 2025-12-02 6:07 ` Nick Hu
2025-12-03 14:16 ` Anup Patel
` (2 more replies)
2026-02-20 4:10 ` [PATCH v3 0/2] riscv-imsic/aplic: Preserve IMSIC and APLIC states during suspend patchwork-bot+linux-riscv
2 siblings, 3 replies; 8+ messages in thread
From: Nick Hu @ 2025-12-02 6:07 UTC (permalink / raw)
To: Anup Patel, Thomas Gleixner, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti
Cc: linux-riscv, linux-kernel, Yong-Xuan Wang, Cyan Yang, Nutty Liu, Nick Hu
The APLIC states might be reset when the platform enters a low power
state, but the register states are not being preserved and restored,
which prevents interrupt delivery after the platform resumes.
Solve this by adding a syscore ops and a power management notifier to
preserve and restore the APLIC states on suspend and resume.
Reviewed-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Cyan Yang <cyan.yang@sifive.com>
Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com>
Signed-off-by: Nick Hu <nick.hu@sifive.com>
---
drivers/irqchip/irq-riscv-aplic-direct.c | 10 ++
drivers/irqchip/irq-riscv-aplic-main.c | 166 ++++++++++++++++++++++++++++++-
drivers/irqchip/irq-riscv-aplic-main.h | 19 ++++
3 files changed, 194 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-riscv-aplic-direct.c b/drivers/irqchip/irq-riscv-aplic-direct.c
index c2a75bf3d20c64c1e1f0e863486633071ab115a7..5a9650225dd805539a2cdf7ca64c7addb4fea39d 100644
--- a/drivers/irqchip/irq-riscv-aplic-direct.c
+++ b/drivers/irqchip/irq-riscv-aplic-direct.c
@@ -8,6 +8,7 @@
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/cpu.h>
+#include <linux/cpumask.h>
#include <linux/interrupt.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
@@ -171,6 +172,15 @@ static void aplic_idc_set_delivery(struct aplic_idc *idc, bool en)
writel(de, idc->regs + APLIC_IDC_IDELIVERY);
}
+void aplic_direct_restore_states(struct aplic_priv *priv)
+{
+ struct aplic_direct *direct = container_of(priv, struct aplic_direct, priv);
+ int cpu;
+
+ for_each_cpu(cpu, &direct->lmask)
+ aplic_idc_set_delivery(per_cpu_ptr(&aplic_idcs, cpu), true);
+}
+
static int aplic_direct_dying_cpu(unsigned int cpu)
{
if (aplic_direct_parent_irq)
diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-riscv-aplic-main.c
index 93e7c51f944abe4cb96fc7427c1f36ab7d2cbc4d..b760942e57f916d86b2d424dca8a3c6008f064e6 100644
--- a/drivers/irqchip/irq-riscv-aplic-main.c
+++ b/drivers/irqchip/irq-riscv-aplic-main.c
@@ -12,10 +12,165 @@
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
#include <linux/printk.h>
+#include <linux/syscore_ops.h>
#include "irq-riscv-aplic-main.h"
+static LIST_HEAD(aplics);
+
+static void aplic_restore_states(struct aplic_priv *priv)
+{
+ struct aplic_saved_regs *saved_regs = &priv->saved_hw_regs;
+ struct aplic_src_ctrl *srcs;
+ void __iomem *regs;
+ u32 nr_irqs, i;
+
+ regs = priv->regs;
+ writel(saved_regs->domaincfg, regs + APLIC_DOMAINCFG);
+#ifdef CONFIG_RISCV_M_MODE
+ writel(saved_regs->msiaddr, regs + APLIC_xMSICFGADDR);
+ writel(saved_regs->msiaddrh, regs + APLIC_xMSICFGADDRH);
+#endif
+ /*
+ * The sourcecfg[i] has to be restored prior to the target[i], interrupt-pending and
+ * interrupt-enable bits. The AIA specification states that "Whenever interrupt source i is
+ * inactive in an interrupt domain, the corresponding interrupt-pending and interrupt-enable
+ * bits within the domain are read-only zeros, and register target[i] is also read-only
+ * zero."
+ */
+ nr_irqs = priv->nr_irqs;
+ for (i = 0; i < nr_irqs; i++) {
+ srcs = &priv->saved_hw_regs.srcs[i];
+ writel(srcs->sourcecfg, regs + APLIC_SOURCECFG_BASE + i * sizeof(u32));
+ writel(srcs->target, regs + APLIC_TARGET_BASE + i * sizeof(u32));
+ }
+
+ for (i = 0; i <= nr_irqs; i += 32) {
+ srcs = &priv->saved_hw_regs.srcs[i];
+ writel(-1U, regs + APLIC_CLRIE_BASE + (i / 32) * sizeof(u32));
+ writel(srcs->ie, regs + APLIC_SETIE_BASE + (i / 32) * sizeof(u32));
+
+ /* Re-trigger the interrupts if it forwards interrupts to target harts by MSIs */
+ if (!priv->nr_idcs)
+ writel(readl(regs + APLIC_CLRIP_BASE + (i / 32) * sizeof(u32)),
+ regs + APLIC_SETIP_BASE + (i / 32) * sizeof(u32));
+ }
+
+ if (priv->nr_idcs)
+ aplic_direct_restore_states(priv);
+}
+
+static void aplic_save_states(struct aplic_priv *priv)
+{
+ struct aplic_src_ctrl *srcs;
+ void __iomem *regs;
+ u32 i, nr_irqs;
+
+ regs = priv->regs;
+ nr_irqs = priv->nr_irqs;
+ /* The valid interrupt source IDs range from 1 to N, where N is priv->nr_irqs */
+ for (i = 0; i < nr_irqs; i++) {
+ srcs = &priv->saved_hw_regs.srcs[i];
+ srcs->target = readl(regs + APLIC_TARGET_BASE + i * sizeof(u32));
+
+ if (i % 32)
+ continue;
+
+ srcs->ie = readl(regs + APLIC_SETIE_BASE + (i / 32) * sizeof(u32));
+ }
+
+ /* Save the nr_irqs bit if needed */
+ if (!(nr_irqs % 32)) {
+ srcs = &priv->saved_hw_regs.srcs[nr_irqs];
+ srcs->ie = readl(regs + APLIC_SETIE_BASE + (nr_irqs / 32) * sizeof(u32));
+ }
+}
+
+static int aplic_syscore_suspend(void)
+{
+ struct aplic_priv *priv;
+
+ list_for_each_entry(priv, &aplics, head)
+ aplic_save_states(priv);
+
+ return 0;
+}
+
+static void aplic_syscore_resume(void)
+{
+ struct aplic_priv *priv;
+
+ list_for_each_entry(priv, &aplics, head)
+ aplic_restore_states(priv);
+}
+
+static struct syscore_ops aplic_syscore_ops = {
+ .suspend = aplic_syscore_suspend,
+ .resume = aplic_syscore_resume,
+};
+
+static int aplic_pm_notifier(struct notifier_block *nb, unsigned long action, void *data)
+{
+ struct aplic_priv *priv = container_of(nb, struct aplic_priv, genpd_nb);
+
+ switch (action) {
+ case GENPD_NOTIFY_PRE_OFF:
+ aplic_save_states(priv);
+ break;
+ case GENPD_NOTIFY_ON:
+ aplic_restore_states(priv);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static void aplic_pm_remove(void *data)
+{
+ struct aplic_priv *priv = data;
+ struct device *dev = priv->dev;
+
+ list_del(&priv->head);
+ if (dev->pm_domain)
+ dev_pm_genpd_remove_notifier(dev);
+}
+
+static int aplic_pm_add(struct device *dev, struct aplic_priv *priv)
+{
+ struct aplic_src_ctrl *srcs;
+ int ret;
+
+ srcs = devm_kzalloc(dev, (priv->nr_irqs + 1) * sizeof(*srcs), GFP_KERNEL);
+ if (!srcs)
+ return -ENOMEM;
+
+ priv->saved_hw_regs.srcs = srcs;
+ list_add(&priv->head, &aplics);
+ if (dev->pm_domain) {
+ priv->genpd_nb.notifier_call = aplic_pm_notifier;
+ ret = dev_pm_genpd_add_notifier(dev, &priv->genpd_nb);
+ if (ret)
+ goto remove_head;
+
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ goto remove_notifier;
+ }
+
+ return devm_add_action_or_reset(dev, aplic_pm_remove, priv);
+
+remove_notifier:
+ dev_pm_genpd_remove_notifier(dev);
+remove_head:
+ list_del(&priv->head);
+ return ret;
+}
+
void aplic_irq_unmask(struct irq_data *d)
{
struct aplic_priv *priv = irq_data_get_irq_chip_data(d);
@@ -60,6 +215,8 @@ int aplic_irq_set_type(struct irq_data *d, unsigned int type)
sourcecfg += (d->hwirq - 1) * sizeof(u32);
writel(val, sourcecfg);
+ priv->saved_hw_regs.srcs[d->hwirq - 1].sourcecfg = val;
+
return 0;
}
@@ -82,6 +239,7 @@ int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base,
void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode)
{
+ struct aplic_saved_regs *saved_regs = &priv->saved_hw_regs;
u32 val;
#ifdef CONFIG_RISCV_M_MODE
u32 valh;
@@ -95,6 +253,8 @@ void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode)
valh |= FIELD_PREP(APLIC_xMSICFGADDRH_HHXS, priv->msicfg.hhxs);
writel(val, priv->regs + APLIC_xMSICFGADDR);
writel(valh, priv->regs + APLIC_xMSICFGADDRH);
+ saved_regs->msiaddr = val;
+ saved_regs->msiaddrh = valh;
}
#endif
@@ -106,6 +266,8 @@ void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode)
writel(val, priv->regs + APLIC_DOMAINCFG);
if (readl(priv->regs + APLIC_DOMAINCFG) != val)
dev_warn(priv->dev, "unable to write 0x%x in domaincfg\n", val);
+
+ saved_regs->domaincfg = val;
}
static void aplic_init_hw_irqs(struct aplic_priv *priv)
@@ -176,7 +338,7 @@ int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, void __iomem *
/* Setup initial state APLIC interrupts */
aplic_init_hw_irqs(priv);
- return 0;
+ return aplic_pm_add(dev, priv);
}
static int aplic_probe(struct platform_device *pdev)
@@ -209,6 +371,8 @@ static int aplic_probe(struct platform_device *pdev)
if (rc)
dev_err_probe(dev, rc, "failed to setup APLIC in %s mode\n",
msi_mode ? "MSI" : "direct");
+ else
+ register_syscore_ops(&aplic_syscore_ops);
#ifdef CONFIG_ACPI
if (!acpi_disabled)
diff --git a/drivers/irqchip/irq-riscv-aplic-main.h b/drivers/irqchip/irq-riscv-aplic-main.h
index b0ad8cde69b1314c6db5ef3cc7070c843c381790..2d8ad7138541ad68a08349d9ed59a2554e520753 100644
--- a/drivers/irqchip/irq-riscv-aplic-main.h
+++ b/drivers/irqchip/irq-riscv-aplic-main.h
@@ -23,7 +23,25 @@ struct aplic_msicfg {
u32 lhxw;
};
+struct aplic_src_ctrl {
+ u32 sourcecfg;
+ u32 target;
+ u32 ie;
+};
+
+struct aplic_saved_regs {
+ u32 domaincfg;
+#ifdef CONFIG_RISCV_M_MODE
+ u32 msiaddr;
+ u32 msiaddrh;
+#endif
+ struct aplic_src_ctrl *srcs;
+};
+
struct aplic_priv {
+ struct list_head head;
+ struct notifier_block genpd_nb;
+ struct aplic_saved_regs saved_hw_regs;
struct device *dev;
u32 gsi_base;
u32 nr_irqs;
@@ -40,6 +58,7 @@ int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base,
unsigned long *hwirq, unsigned int *type);
void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode);
int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, void __iomem *regs);
+void aplic_direct_restore_states(struct aplic_priv *priv);
int aplic_direct_setup(struct device *dev, void __iomem *regs);
#ifdef CONFIG_RISCV_APLIC_MSI
int aplic_msi_setup(struct device *dev, void __iomem *regs);
--
2.34.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 2/2] irqchip/riscv-aplic: Preserve APLIC states across suspend/resume
2025-12-02 6:07 ` [PATCH v3 2/2] irqchip/riscv-aplic: Preserve APLIC states across suspend/resume Nick Hu
@ 2025-12-03 14:16 ` Anup Patel
2025-12-15 21:46 ` [tip: irq/drivers] " tip-bot2 for Nick Hu
2025-12-17 17:36 ` tip-bot2 for Nick Hu
2 siblings, 0 replies; 8+ messages in thread
From: Anup Patel @ 2025-12-03 14:16 UTC (permalink / raw)
To: Nick Hu
Cc: Thomas Gleixner, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, linux-riscv, linux-kernel, Yong-Xuan Wang,
Cyan Yang, Nutty Liu
On Tue, Dec 2, 2025 at 11:31 AM Nick Hu <nick.hu@sifive.com> wrote:
>
> The APLIC states might be reset when the platform enters a low power
> state, but the register states are not being preserved and restored,
> which prevents interrupt delivery after the platform resumes.
> Solve this by adding a syscore ops and a power management notifier to
> preserve and restore the APLIC states on suspend and resume.
>
> Reviewed-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> Reviewed-by: Cyan Yang <cyan.yang@sifive.com>
> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com>
> Signed-off-by: Nick Hu <nick.hu@sifive.com>
LGTM.
Reviewed-by: Anup Patel <anup@brainfault.org>
Thanks,
Anup
> ---
> drivers/irqchip/irq-riscv-aplic-direct.c | 10 ++
> drivers/irqchip/irq-riscv-aplic-main.c | 166 ++++++++++++++++++++++++++++++-
> drivers/irqchip/irq-riscv-aplic-main.h | 19 ++++
> 3 files changed, 194 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-riscv-aplic-direct.c b/drivers/irqchip/irq-riscv-aplic-direct.c
> index c2a75bf3d20c64c1e1f0e863486633071ab115a7..5a9650225dd805539a2cdf7ca64c7addb4fea39d 100644
> --- a/drivers/irqchip/irq-riscv-aplic-direct.c
> +++ b/drivers/irqchip/irq-riscv-aplic-direct.c
> @@ -8,6 +8,7 @@
> #include <linux/bitfield.h>
> #include <linux/bitops.h>
> #include <linux/cpu.h>
> +#include <linux/cpumask.h>
> #include <linux/interrupt.h>
> #include <linux/irqchip.h>
> #include <linux/irqchip/chained_irq.h>
> @@ -171,6 +172,15 @@ static void aplic_idc_set_delivery(struct aplic_idc *idc, bool en)
> writel(de, idc->regs + APLIC_IDC_IDELIVERY);
> }
>
> +void aplic_direct_restore_states(struct aplic_priv *priv)
> +{
> + struct aplic_direct *direct = container_of(priv, struct aplic_direct, priv);
> + int cpu;
> +
> + for_each_cpu(cpu, &direct->lmask)
> + aplic_idc_set_delivery(per_cpu_ptr(&aplic_idcs, cpu), true);
> +}
> +
> static int aplic_direct_dying_cpu(unsigned int cpu)
> {
> if (aplic_direct_parent_irq)
> diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-riscv-aplic-main.c
> index 93e7c51f944abe4cb96fc7427c1f36ab7d2cbc4d..b760942e57f916d86b2d424dca8a3c6008f064e6 100644
> --- a/drivers/irqchip/irq-riscv-aplic-main.c
> +++ b/drivers/irqchip/irq-riscv-aplic-main.c
> @@ -12,10 +12,165 @@
> #include <linux/of.h>
> #include <linux/of_irq.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> +#include <linux/pm_runtime.h>
> #include <linux/printk.h>
> +#include <linux/syscore_ops.h>
>
> #include "irq-riscv-aplic-main.h"
>
> +static LIST_HEAD(aplics);
> +
> +static void aplic_restore_states(struct aplic_priv *priv)
> +{
> + struct aplic_saved_regs *saved_regs = &priv->saved_hw_regs;
> + struct aplic_src_ctrl *srcs;
> + void __iomem *regs;
> + u32 nr_irqs, i;
> +
> + regs = priv->regs;
> + writel(saved_regs->domaincfg, regs + APLIC_DOMAINCFG);
> +#ifdef CONFIG_RISCV_M_MODE
> + writel(saved_regs->msiaddr, regs + APLIC_xMSICFGADDR);
> + writel(saved_regs->msiaddrh, regs + APLIC_xMSICFGADDRH);
> +#endif
> + /*
> + * The sourcecfg[i] has to be restored prior to the target[i], interrupt-pending and
> + * interrupt-enable bits. The AIA specification states that "Whenever interrupt source i is
> + * inactive in an interrupt domain, the corresponding interrupt-pending and interrupt-enable
> + * bits within the domain are read-only zeros, and register target[i] is also read-only
> + * zero."
> + */
> + nr_irqs = priv->nr_irqs;
> + for (i = 0; i < nr_irqs; i++) {
> + srcs = &priv->saved_hw_regs.srcs[i];
> + writel(srcs->sourcecfg, regs + APLIC_SOURCECFG_BASE + i * sizeof(u32));
> + writel(srcs->target, regs + APLIC_TARGET_BASE + i * sizeof(u32));
> + }
> +
> + for (i = 0; i <= nr_irqs; i += 32) {
> + srcs = &priv->saved_hw_regs.srcs[i];
> + writel(-1U, regs + APLIC_CLRIE_BASE + (i / 32) * sizeof(u32));
> + writel(srcs->ie, regs + APLIC_SETIE_BASE + (i / 32) * sizeof(u32));
> +
> + /* Re-trigger the interrupts if it forwards interrupts to target harts by MSIs */
> + if (!priv->nr_idcs)
> + writel(readl(regs + APLIC_CLRIP_BASE + (i / 32) * sizeof(u32)),
> + regs + APLIC_SETIP_BASE + (i / 32) * sizeof(u32));
> + }
> +
> + if (priv->nr_idcs)
> + aplic_direct_restore_states(priv);
> +}
> +
> +static void aplic_save_states(struct aplic_priv *priv)
> +{
> + struct aplic_src_ctrl *srcs;
> + void __iomem *regs;
> + u32 i, nr_irqs;
> +
> + regs = priv->regs;
> + nr_irqs = priv->nr_irqs;
> + /* The valid interrupt source IDs range from 1 to N, where N is priv->nr_irqs */
> + for (i = 0; i < nr_irqs; i++) {
> + srcs = &priv->saved_hw_regs.srcs[i];
> + srcs->target = readl(regs + APLIC_TARGET_BASE + i * sizeof(u32));
> +
> + if (i % 32)
> + continue;
> +
> + srcs->ie = readl(regs + APLIC_SETIE_BASE + (i / 32) * sizeof(u32));
> + }
> +
> + /* Save the nr_irqs bit if needed */
> + if (!(nr_irqs % 32)) {
> + srcs = &priv->saved_hw_regs.srcs[nr_irqs];
> + srcs->ie = readl(regs + APLIC_SETIE_BASE + (nr_irqs / 32) * sizeof(u32));
> + }
> +}
> +
> +static int aplic_syscore_suspend(void)
> +{
> + struct aplic_priv *priv;
> +
> + list_for_each_entry(priv, &aplics, head)
> + aplic_save_states(priv);
> +
> + return 0;
> +}
> +
> +static void aplic_syscore_resume(void)
> +{
> + struct aplic_priv *priv;
> +
> + list_for_each_entry(priv, &aplics, head)
> + aplic_restore_states(priv);
> +}
> +
> +static struct syscore_ops aplic_syscore_ops = {
> + .suspend = aplic_syscore_suspend,
> + .resume = aplic_syscore_resume,
> +};
> +
> +static int aplic_pm_notifier(struct notifier_block *nb, unsigned long action, void *data)
> +{
> + struct aplic_priv *priv = container_of(nb, struct aplic_priv, genpd_nb);
> +
> + switch (action) {
> + case GENPD_NOTIFY_PRE_OFF:
> + aplic_save_states(priv);
> + break;
> + case GENPD_NOTIFY_ON:
> + aplic_restore_states(priv);
> + break;
> + default:
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static void aplic_pm_remove(void *data)
> +{
> + struct aplic_priv *priv = data;
> + struct device *dev = priv->dev;
> +
> + list_del(&priv->head);
> + if (dev->pm_domain)
> + dev_pm_genpd_remove_notifier(dev);
> +}
> +
> +static int aplic_pm_add(struct device *dev, struct aplic_priv *priv)
> +{
> + struct aplic_src_ctrl *srcs;
> + int ret;
> +
> + srcs = devm_kzalloc(dev, (priv->nr_irqs + 1) * sizeof(*srcs), GFP_KERNEL);
> + if (!srcs)
> + return -ENOMEM;
> +
> + priv->saved_hw_regs.srcs = srcs;
> + list_add(&priv->head, &aplics);
> + if (dev->pm_domain) {
> + priv->genpd_nb.notifier_call = aplic_pm_notifier;
> + ret = dev_pm_genpd_add_notifier(dev, &priv->genpd_nb);
> + if (ret)
> + goto remove_head;
> +
> + ret = devm_pm_runtime_enable(dev);
> + if (ret)
> + goto remove_notifier;
> + }
> +
> + return devm_add_action_or_reset(dev, aplic_pm_remove, priv);
> +
> +remove_notifier:
> + dev_pm_genpd_remove_notifier(dev);
> +remove_head:
> + list_del(&priv->head);
> + return ret;
> +}
> +
> void aplic_irq_unmask(struct irq_data *d)
> {
> struct aplic_priv *priv = irq_data_get_irq_chip_data(d);
> @@ -60,6 +215,8 @@ int aplic_irq_set_type(struct irq_data *d, unsigned int type)
> sourcecfg += (d->hwirq - 1) * sizeof(u32);
> writel(val, sourcecfg);
>
> + priv->saved_hw_regs.srcs[d->hwirq - 1].sourcecfg = val;
> +
> return 0;
> }
>
> @@ -82,6 +239,7 @@ int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base,
>
> void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode)
> {
> + struct aplic_saved_regs *saved_regs = &priv->saved_hw_regs;
> u32 val;
> #ifdef CONFIG_RISCV_M_MODE
> u32 valh;
> @@ -95,6 +253,8 @@ void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode)
> valh |= FIELD_PREP(APLIC_xMSICFGADDRH_HHXS, priv->msicfg.hhxs);
> writel(val, priv->regs + APLIC_xMSICFGADDR);
> writel(valh, priv->regs + APLIC_xMSICFGADDRH);
> + saved_regs->msiaddr = val;
> + saved_regs->msiaddrh = valh;
> }
> #endif
>
> @@ -106,6 +266,8 @@ void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode)
> writel(val, priv->regs + APLIC_DOMAINCFG);
> if (readl(priv->regs + APLIC_DOMAINCFG) != val)
> dev_warn(priv->dev, "unable to write 0x%x in domaincfg\n", val);
> +
> + saved_regs->domaincfg = val;
> }
>
> static void aplic_init_hw_irqs(struct aplic_priv *priv)
> @@ -176,7 +338,7 @@ int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, void __iomem *
> /* Setup initial state APLIC interrupts */
> aplic_init_hw_irqs(priv);
>
> - return 0;
> + return aplic_pm_add(dev, priv);
> }
>
> static int aplic_probe(struct platform_device *pdev)
> @@ -209,6 +371,8 @@ static int aplic_probe(struct platform_device *pdev)
> if (rc)
> dev_err_probe(dev, rc, "failed to setup APLIC in %s mode\n",
> msi_mode ? "MSI" : "direct");
> + else
> + register_syscore_ops(&aplic_syscore_ops);
>
> #ifdef CONFIG_ACPI
> if (!acpi_disabled)
> diff --git a/drivers/irqchip/irq-riscv-aplic-main.h b/drivers/irqchip/irq-riscv-aplic-main.h
> index b0ad8cde69b1314c6db5ef3cc7070c843c381790..2d8ad7138541ad68a08349d9ed59a2554e520753 100644
> --- a/drivers/irqchip/irq-riscv-aplic-main.h
> +++ b/drivers/irqchip/irq-riscv-aplic-main.h
> @@ -23,7 +23,25 @@ struct aplic_msicfg {
> u32 lhxw;
> };
>
> +struct aplic_src_ctrl {
> + u32 sourcecfg;
> + u32 target;
> + u32 ie;
> +};
> +
> +struct aplic_saved_regs {
> + u32 domaincfg;
> +#ifdef CONFIG_RISCV_M_MODE
> + u32 msiaddr;
> + u32 msiaddrh;
> +#endif
> + struct aplic_src_ctrl *srcs;
> +};
> +
> struct aplic_priv {
> + struct list_head head;
> + struct notifier_block genpd_nb;
> + struct aplic_saved_regs saved_hw_regs;
> struct device *dev;
> u32 gsi_base;
> u32 nr_irqs;
> @@ -40,6 +58,7 @@ int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base,
> unsigned long *hwirq, unsigned int *type);
> void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode);
> int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, void __iomem *regs);
> +void aplic_direct_restore_states(struct aplic_priv *priv);
> int aplic_direct_setup(struct device *dev, void __iomem *regs);
> #ifdef CONFIG_RISCV_APLIC_MSI
> int aplic_msi_setup(struct device *dev, void __iomem *regs);
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [tip: irq/drivers] irqchip/riscv-aplic: Preserve APLIC states across suspend/resume
2025-12-02 6:07 ` [PATCH v3 2/2] irqchip/riscv-aplic: Preserve APLIC states across suspend/resume Nick Hu
2025-12-03 14:16 ` Anup Patel
@ 2025-12-15 21:46 ` tip-bot2 for Nick Hu
2025-12-17 17:36 ` tip-bot2 for Nick Hu
2 siblings, 0 replies; 8+ messages in thread
From: tip-bot2 for Nick Hu @ 2025-12-15 21:46 UTC (permalink / raw)
To: linux-tip-commits
Cc: Nick Hu, Thomas Gleixner, Yong-Xuan Wang, Cyan Yang, Nutty Liu,
Anup Patel, x86, linux-kernel
The following commit has been merged into the irq/drivers branch of tip:
Commit-ID: 1c546bb4336188439c8486bd7472d4aa7b6d3585
Gitweb: https://git.kernel.org/tip/1c546bb4336188439c8486bd7472d4aa7b6d3585
Author: Nick Hu <nick.hu@sifive.com>
AuthorDate: Tue, 02 Dec 2025 14:07:41 +08:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Mon, 15 Dec 2025 22:44:33 +01:00
irqchip/riscv-aplic: Preserve APLIC states across suspend/resume
The APLIC states might be reset when the platform enters a low power
state, but the register states are not being preserved and restored,
which prevents interrupt delivery after the platform resumes.
Solve this by adding a syscore ops and a power management notifier to
preserve and restore the APLIC states on suspend and resume.
Signed-off-by: Nick Hu <nick.hu@sifive.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Cyan Yang <cyan.yang@sifive.com>
Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://patch.msgid.link/20251202-preserve-aplic-imsic-v3-2-1844fbf1fe92@sifive.com
---
drivers/irqchip/irq-riscv-aplic-direct.c | 10 +-
drivers/irqchip/irq-riscv-aplic-main.c | 166 +++++++++++++++++++++-
drivers/irqchip/irq-riscv-aplic-main.h | 19 +++-
3 files changed, 194 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-riscv-aplic-direct.c b/drivers/irqchip/irq-riscv-aplic-direct.c
index c2a75bf..5a96502 100644
--- a/drivers/irqchip/irq-riscv-aplic-direct.c
+++ b/drivers/irqchip/irq-riscv-aplic-direct.c
@@ -8,6 +8,7 @@
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/cpu.h>
+#include <linux/cpumask.h>
#include <linux/interrupt.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
@@ -171,6 +172,15 @@ static void aplic_idc_set_delivery(struct aplic_idc *idc, bool en)
writel(de, idc->regs + APLIC_IDC_IDELIVERY);
}
+void aplic_direct_restore_states(struct aplic_priv *priv)
+{
+ struct aplic_direct *direct = container_of(priv, struct aplic_direct, priv);
+ int cpu;
+
+ for_each_cpu(cpu, &direct->lmask)
+ aplic_idc_set_delivery(per_cpu_ptr(&aplic_idcs, cpu), true);
+}
+
static int aplic_direct_dying_cpu(unsigned int cpu)
{
if (aplic_direct_parent_irq)
diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-riscv-aplic-main.c
index 93e7c51..b760942 100644
--- a/drivers/irqchip/irq-riscv-aplic-main.c
+++ b/drivers/irqchip/irq-riscv-aplic-main.c
@@ -12,10 +12,165 @@
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
#include <linux/printk.h>
+#include <linux/syscore_ops.h>
#include "irq-riscv-aplic-main.h"
+static LIST_HEAD(aplics);
+
+static void aplic_restore_states(struct aplic_priv *priv)
+{
+ struct aplic_saved_regs *saved_regs = &priv->saved_hw_regs;
+ struct aplic_src_ctrl *srcs;
+ void __iomem *regs;
+ u32 nr_irqs, i;
+
+ regs = priv->regs;
+ writel(saved_regs->domaincfg, regs + APLIC_DOMAINCFG);
+#ifdef CONFIG_RISCV_M_MODE
+ writel(saved_regs->msiaddr, regs + APLIC_xMSICFGADDR);
+ writel(saved_regs->msiaddrh, regs + APLIC_xMSICFGADDRH);
+#endif
+ /*
+ * The sourcecfg[i] has to be restored prior to the target[i], interrupt-pending and
+ * interrupt-enable bits. The AIA specification states that "Whenever interrupt source i is
+ * inactive in an interrupt domain, the corresponding interrupt-pending and interrupt-enable
+ * bits within the domain are read-only zeros, and register target[i] is also read-only
+ * zero."
+ */
+ nr_irqs = priv->nr_irqs;
+ for (i = 0; i < nr_irqs; i++) {
+ srcs = &priv->saved_hw_regs.srcs[i];
+ writel(srcs->sourcecfg, regs + APLIC_SOURCECFG_BASE + i * sizeof(u32));
+ writel(srcs->target, regs + APLIC_TARGET_BASE + i * sizeof(u32));
+ }
+
+ for (i = 0; i <= nr_irqs; i += 32) {
+ srcs = &priv->saved_hw_regs.srcs[i];
+ writel(-1U, regs + APLIC_CLRIE_BASE + (i / 32) * sizeof(u32));
+ writel(srcs->ie, regs + APLIC_SETIE_BASE + (i / 32) * sizeof(u32));
+
+ /* Re-trigger the interrupts if it forwards interrupts to target harts by MSIs */
+ if (!priv->nr_idcs)
+ writel(readl(regs + APLIC_CLRIP_BASE + (i / 32) * sizeof(u32)),
+ regs + APLIC_SETIP_BASE + (i / 32) * sizeof(u32));
+ }
+
+ if (priv->nr_idcs)
+ aplic_direct_restore_states(priv);
+}
+
+static void aplic_save_states(struct aplic_priv *priv)
+{
+ struct aplic_src_ctrl *srcs;
+ void __iomem *regs;
+ u32 i, nr_irqs;
+
+ regs = priv->regs;
+ nr_irqs = priv->nr_irqs;
+ /* The valid interrupt source IDs range from 1 to N, where N is priv->nr_irqs */
+ for (i = 0; i < nr_irqs; i++) {
+ srcs = &priv->saved_hw_regs.srcs[i];
+ srcs->target = readl(regs + APLIC_TARGET_BASE + i * sizeof(u32));
+
+ if (i % 32)
+ continue;
+
+ srcs->ie = readl(regs + APLIC_SETIE_BASE + (i / 32) * sizeof(u32));
+ }
+
+ /* Save the nr_irqs bit if needed */
+ if (!(nr_irqs % 32)) {
+ srcs = &priv->saved_hw_regs.srcs[nr_irqs];
+ srcs->ie = readl(regs + APLIC_SETIE_BASE + (nr_irqs / 32) * sizeof(u32));
+ }
+}
+
+static int aplic_syscore_suspend(void)
+{
+ struct aplic_priv *priv;
+
+ list_for_each_entry(priv, &aplics, head)
+ aplic_save_states(priv);
+
+ return 0;
+}
+
+static void aplic_syscore_resume(void)
+{
+ struct aplic_priv *priv;
+
+ list_for_each_entry(priv, &aplics, head)
+ aplic_restore_states(priv);
+}
+
+static struct syscore_ops aplic_syscore_ops = {
+ .suspend = aplic_syscore_suspend,
+ .resume = aplic_syscore_resume,
+};
+
+static int aplic_pm_notifier(struct notifier_block *nb, unsigned long action, void *data)
+{
+ struct aplic_priv *priv = container_of(nb, struct aplic_priv, genpd_nb);
+
+ switch (action) {
+ case GENPD_NOTIFY_PRE_OFF:
+ aplic_save_states(priv);
+ break;
+ case GENPD_NOTIFY_ON:
+ aplic_restore_states(priv);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static void aplic_pm_remove(void *data)
+{
+ struct aplic_priv *priv = data;
+ struct device *dev = priv->dev;
+
+ list_del(&priv->head);
+ if (dev->pm_domain)
+ dev_pm_genpd_remove_notifier(dev);
+}
+
+static int aplic_pm_add(struct device *dev, struct aplic_priv *priv)
+{
+ struct aplic_src_ctrl *srcs;
+ int ret;
+
+ srcs = devm_kzalloc(dev, (priv->nr_irqs + 1) * sizeof(*srcs), GFP_KERNEL);
+ if (!srcs)
+ return -ENOMEM;
+
+ priv->saved_hw_regs.srcs = srcs;
+ list_add(&priv->head, &aplics);
+ if (dev->pm_domain) {
+ priv->genpd_nb.notifier_call = aplic_pm_notifier;
+ ret = dev_pm_genpd_add_notifier(dev, &priv->genpd_nb);
+ if (ret)
+ goto remove_head;
+
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ goto remove_notifier;
+ }
+
+ return devm_add_action_or_reset(dev, aplic_pm_remove, priv);
+
+remove_notifier:
+ dev_pm_genpd_remove_notifier(dev);
+remove_head:
+ list_del(&priv->head);
+ return ret;
+}
+
void aplic_irq_unmask(struct irq_data *d)
{
struct aplic_priv *priv = irq_data_get_irq_chip_data(d);
@@ -60,6 +215,8 @@ int aplic_irq_set_type(struct irq_data *d, unsigned int type)
sourcecfg += (d->hwirq - 1) * sizeof(u32);
writel(val, sourcecfg);
+ priv->saved_hw_regs.srcs[d->hwirq - 1].sourcecfg = val;
+
return 0;
}
@@ -82,6 +239,7 @@ int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base,
void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode)
{
+ struct aplic_saved_regs *saved_regs = &priv->saved_hw_regs;
u32 val;
#ifdef CONFIG_RISCV_M_MODE
u32 valh;
@@ -95,6 +253,8 @@ void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode)
valh |= FIELD_PREP(APLIC_xMSICFGADDRH_HHXS, priv->msicfg.hhxs);
writel(val, priv->regs + APLIC_xMSICFGADDR);
writel(valh, priv->regs + APLIC_xMSICFGADDRH);
+ saved_regs->msiaddr = val;
+ saved_regs->msiaddrh = valh;
}
#endif
@@ -106,6 +266,8 @@ void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode)
writel(val, priv->regs + APLIC_DOMAINCFG);
if (readl(priv->regs + APLIC_DOMAINCFG) != val)
dev_warn(priv->dev, "unable to write 0x%x in domaincfg\n", val);
+
+ saved_regs->domaincfg = val;
}
static void aplic_init_hw_irqs(struct aplic_priv *priv)
@@ -176,7 +338,7 @@ int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, void __iomem *
/* Setup initial state APLIC interrupts */
aplic_init_hw_irqs(priv);
- return 0;
+ return aplic_pm_add(dev, priv);
}
static int aplic_probe(struct platform_device *pdev)
@@ -209,6 +371,8 @@ static int aplic_probe(struct platform_device *pdev)
if (rc)
dev_err_probe(dev, rc, "failed to setup APLIC in %s mode\n",
msi_mode ? "MSI" : "direct");
+ else
+ register_syscore_ops(&aplic_syscore_ops);
#ifdef CONFIG_ACPI
if (!acpi_disabled)
diff --git a/drivers/irqchip/irq-riscv-aplic-main.h b/drivers/irqchip/irq-riscv-aplic-main.h
index b0ad8cd..2d8ad71 100644
--- a/drivers/irqchip/irq-riscv-aplic-main.h
+++ b/drivers/irqchip/irq-riscv-aplic-main.h
@@ -23,7 +23,25 @@ struct aplic_msicfg {
u32 lhxw;
};
+struct aplic_src_ctrl {
+ u32 sourcecfg;
+ u32 target;
+ u32 ie;
+};
+
+struct aplic_saved_regs {
+ u32 domaincfg;
+#ifdef CONFIG_RISCV_M_MODE
+ u32 msiaddr;
+ u32 msiaddrh;
+#endif
+ struct aplic_src_ctrl *srcs;
+};
+
struct aplic_priv {
+ struct list_head head;
+ struct notifier_block genpd_nb;
+ struct aplic_saved_regs saved_hw_regs;
struct device *dev;
u32 gsi_base;
u32 nr_irqs;
@@ -40,6 +58,7 @@ int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base,
unsigned long *hwirq, unsigned int *type);
void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode);
int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, void __iomem *regs);
+void aplic_direct_restore_states(struct aplic_priv *priv);
int aplic_direct_setup(struct device *dev, void __iomem *regs);
#ifdef CONFIG_RISCV_APLIC_MSI
int aplic_msi_setup(struct device *dev, void __iomem *regs);
^ permalink raw reply [flat|nested] 8+ messages in thread
* [tip: irq/drivers] irqchip/riscv-imsic: Add a CPU pm notifier to restore the IMSIC on exit
2025-12-02 6:07 ` [PATCH v3 1/2] irqchip/riscv-imsic: Add a CPU pm notifier to restore the IMSIC on exit Nick Hu
@ 2025-12-15 21:46 ` tip-bot2 for Nick Hu
0 siblings, 0 replies; 8+ messages in thread
From: tip-bot2 for Nick Hu @ 2025-12-15 21:46 UTC (permalink / raw)
To: linux-tip-commits
Cc: Nick Hu, Thomas Gleixner, Yong-Xuan Wang, Cyan Yang, Anup Patel,
Nutty Liu, x86, linux-kernel
The following commit has been merged into the irq/drivers branch of tip:
Commit-ID: f48b4bd0915bf61ac12b8c65c7939ebd03bc8abf
Gitweb: https://git.kernel.org/tip/f48b4bd0915bf61ac12b8c65c7939ebd03bc8abf
Author: Nick Hu <nick.hu@sifive.com>
AuthorDate: Tue, 02 Dec 2025 14:07:40 +08:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Mon, 15 Dec 2025 22:44:33 +01:00
irqchip/riscv-imsic: Add a CPU pm notifier to restore the IMSIC on exit
The IMSIC might be reset when the system enters a low power state, but on
exit nothing restores the registers, which prevents interrupt delivery.
Solve this by registering a CPU power management notifier, which restores
the IMSIC on exit.
Signed-off-by: Nick Hu <nick.hu@sifive.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Cyan Yang <cyan.yang@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com>
Link: https://patch.msgid.link/20251202-preserve-aplic-imsic-v3-1-1844fbf1fe92@sifive.com
---
drivers/irqchip/irq-riscv-imsic-early.c | 39 +++++++++++++++++++-----
1 file changed, 31 insertions(+), 8 deletions(-)
diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c
index 6bac67c..ba903fa 100644
--- a/drivers/irqchip/irq-riscv-imsic-early.c
+++ b/drivers/irqchip/irq-riscv-imsic-early.c
@@ -7,6 +7,7 @@
#define pr_fmt(fmt) "riscv-imsic: " fmt
#include <linux/acpi.h>
#include <linux/cpu.h>
+#include <linux/cpu_pm.h>
#include <linux/export.h>
#include <linux/interrupt.h>
#include <linux/init.h>
@@ -123,14 +124,8 @@ static void imsic_handle_irq(struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
-static int imsic_starting_cpu(unsigned int cpu)
+static void imsic_hw_states_init(void)
{
- /* Mark per-CPU IMSIC state as online */
- imsic_state_online();
-
- /* Enable per-CPU parent interrupt */
- enable_percpu_irq(imsic_parent_irq, irq_get_trigger_type(imsic_parent_irq));
-
/* Setup IPIs */
imsic_ipi_starting_cpu();
@@ -142,6 +137,18 @@ static int imsic_starting_cpu(unsigned int cpu)
/* Enable local interrupt delivery */
imsic_local_delivery(true);
+}
+
+static int imsic_starting_cpu(unsigned int cpu)
+{
+ /* Mark per-CPU IMSIC state as online */
+ imsic_state_online();
+
+ /* Enable per-CPU parent interrupt */
+ enable_percpu_irq(imsic_parent_irq, irq_get_trigger_type(imsic_parent_irq));
+
+ /* Initialize the IMSIC registers to enable the interrupt delivery */
+ imsic_hw_states_init();
return 0;
}
@@ -157,6 +164,22 @@ static int imsic_dying_cpu(unsigned int cpu)
return 0;
}
+static int imsic_pm_notifier(struct notifier_block *self, unsigned long cmd, void *v)
+{
+ switch (cmd) {
+ case CPU_PM_EXIT:
+ /* Initialize the IMSIC registers to enable the interrupt delivery */
+ imsic_hw_states_init();
+ break;
+ }
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block imsic_pm_notifier_block = {
+ .notifier_call = imsic_pm_notifier,
+};
+
static int __init imsic_early_probe(struct fwnode_handle *fwnode)
{
struct irq_domain *domain;
@@ -194,7 +217,7 @@ static int __init imsic_early_probe(struct fwnode_handle *fwnode)
cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_IMSIC_STARTING, "irqchip/riscv/imsic:starting",
imsic_starting_cpu, imsic_dying_cpu);
- return 0;
+ return cpu_pm_register_notifier(&imsic_pm_notifier_block);
}
static int __init imsic_early_dt_init(struct device_node *node, struct device_node *parent)
^ permalink raw reply [flat|nested] 8+ messages in thread
* [tip: irq/drivers] irqchip/riscv-aplic: Preserve APLIC states across suspend/resume
2025-12-02 6:07 ` [PATCH v3 2/2] irqchip/riscv-aplic: Preserve APLIC states across suspend/resume Nick Hu
2025-12-03 14:16 ` Anup Patel
2025-12-15 21:46 ` [tip: irq/drivers] " tip-bot2 for Nick Hu
@ 2025-12-17 17:36 ` tip-bot2 for Nick Hu
2 siblings, 0 replies; 8+ messages in thread
From: tip-bot2 for Nick Hu @ 2025-12-17 17:36 UTC (permalink / raw)
To: linux-tip-commits
Cc: Nick Hu, Thomas Gleixner, Yong-Xuan Wang, Cyan Yang, Nutty Liu,
Anup Patel, x86, linux-kernel
The following commit has been merged into the irq/drivers branch of tip:
Commit-ID: 95a8ddde36601d0a645475fb080ed118db59c8c3
Gitweb: https://git.kernel.org/tip/95a8ddde36601d0a645475fb080ed118db59c8c3
Author: Nick Hu <nick.hu@sifive.com>
AuthorDate: Tue, 02 Dec 2025 14:07:41 +08:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Tue, 16 Dec 2025 19:08:43 +01:00
irqchip/riscv-aplic: Preserve APLIC states across suspend/resume
The APLIC states might be reset when the platform enters a low power
state, but the register states are not being preserved and restored,
which prevents interrupt delivery after the platform resumes.
Solve this by adding a syscore ops and a power management notifier to
preserve and restore the APLIC states on suspend and resume.
[ tglx: Folded the build fix provided by Geert ]
Signed-off-by: Nick Hu <nick.hu@sifive.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Cyan Yang <cyan.yang@sifive.com>
Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://patch.msgid.link/20251202-preserve-aplic-imsic-v3-2-1844fbf1fe92@sifive.com
---
drivers/irqchip/irq-riscv-aplic-direct.c | 10 +-
drivers/irqchip/irq-riscv-aplic-main.c | 170 +++++++++++++++++++++-
drivers/irqchip/irq-riscv-aplic-main.h | 19 ++-
3 files changed, 198 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-riscv-aplic-direct.c b/drivers/irqchip/irq-riscv-aplic-direct.c
index c2a75bf..5a96502 100644
--- a/drivers/irqchip/irq-riscv-aplic-direct.c
+++ b/drivers/irqchip/irq-riscv-aplic-direct.c
@@ -8,6 +8,7 @@
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/cpu.h>
+#include <linux/cpumask.h>
#include <linux/interrupt.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
@@ -171,6 +172,15 @@ static void aplic_idc_set_delivery(struct aplic_idc *idc, bool en)
writel(de, idc->regs + APLIC_IDC_IDELIVERY);
}
+void aplic_direct_restore_states(struct aplic_priv *priv)
+{
+ struct aplic_direct *direct = container_of(priv, struct aplic_direct, priv);
+ int cpu;
+
+ for_each_cpu(cpu, &direct->lmask)
+ aplic_idc_set_delivery(per_cpu_ptr(&aplic_idcs, cpu), true);
+}
+
static int aplic_direct_dying_cpu(unsigned int cpu)
{
if (aplic_direct_parent_irq)
diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-riscv-aplic-main.c
index 93e7c51..4495ca2 100644
--- a/drivers/irqchip/irq-riscv-aplic-main.c
+++ b/drivers/irqchip/irq-riscv-aplic-main.c
@@ -12,10 +12,169 @@
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
#include <linux/printk.h>
+#include <linux/syscore_ops.h>
#include "irq-riscv-aplic-main.h"
+static LIST_HEAD(aplics);
+
+static void aplic_restore_states(struct aplic_priv *priv)
+{
+ struct aplic_saved_regs *saved_regs = &priv->saved_hw_regs;
+ struct aplic_src_ctrl *srcs;
+ void __iomem *regs;
+ u32 nr_irqs, i;
+
+ regs = priv->regs;
+ writel(saved_regs->domaincfg, regs + APLIC_DOMAINCFG);
+#ifdef CONFIG_RISCV_M_MODE
+ writel(saved_regs->msiaddr, regs + APLIC_xMSICFGADDR);
+ writel(saved_regs->msiaddrh, regs + APLIC_xMSICFGADDRH);
+#endif
+ /*
+ * The sourcecfg[i] has to be restored prior to the target[i], interrupt-pending and
+ * interrupt-enable bits. The AIA specification states that "Whenever interrupt source i is
+ * inactive in an interrupt domain, the corresponding interrupt-pending and interrupt-enable
+ * bits within the domain are read-only zeros, and register target[i] is also read-only
+ * zero."
+ */
+ nr_irqs = priv->nr_irqs;
+ for (i = 0; i < nr_irqs; i++) {
+ srcs = &priv->saved_hw_regs.srcs[i];
+ writel(srcs->sourcecfg, regs + APLIC_SOURCECFG_BASE + i * sizeof(u32));
+ writel(srcs->target, regs + APLIC_TARGET_BASE + i * sizeof(u32));
+ }
+
+ for (i = 0; i <= nr_irqs; i += 32) {
+ srcs = &priv->saved_hw_regs.srcs[i];
+ writel(-1U, regs + APLIC_CLRIE_BASE + (i / 32) * sizeof(u32));
+ writel(srcs->ie, regs + APLIC_SETIE_BASE + (i / 32) * sizeof(u32));
+
+ /* Re-trigger the interrupts if it forwards interrupts to target harts by MSIs */
+ if (!priv->nr_idcs)
+ writel(readl(regs + APLIC_CLRIP_BASE + (i / 32) * sizeof(u32)),
+ regs + APLIC_SETIP_BASE + (i / 32) * sizeof(u32));
+ }
+
+ if (priv->nr_idcs)
+ aplic_direct_restore_states(priv);
+}
+
+static void aplic_save_states(struct aplic_priv *priv)
+{
+ struct aplic_src_ctrl *srcs;
+ void __iomem *regs;
+ u32 i, nr_irqs;
+
+ regs = priv->regs;
+ nr_irqs = priv->nr_irqs;
+ /* The valid interrupt source IDs range from 1 to N, where N is priv->nr_irqs */
+ for (i = 0; i < nr_irqs; i++) {
+ srcs = &priv->saved_hw_regs.srcs[i];
+ srcs->target = readl(regs + APLIC_TARGET_BASE + i * sizeof(u32));
+
+ if (i % 32)
+ continue;
+
+ srcs->ie = readl(regs + APLIC_SETIE_BASE + (i / 32) * sizeof(u32));
+ }
+
+ /* Save the nr_irqs bit if needed */
+ if (!(nr_irqs % 32)) {
+ srcs = &priv->saved_hw_regs.srcs[nr_irqs];
+ srcs->ie = readl(regs + APLIC_SETIE_BASE + (nr_irqs / 32) * sizeof(u32));
+ }
+}
+
+static int aplic_syscore_suspend(void *data)
+{
+ struct aplic_priv *priv;
+
+ list_for_each_entry(priv, &aplics, head)
+ aplic_save_states(priv);
+
+ return 0;
+}
+
+static void aplic_syscore_resume(void *data)
+{
+ struct aplic_priv *priv;
+
+ list_for_each_entry(priv, &aplics, head)
+ aplic_restore_states(priv);
+}
+
+static struct syscore_ops aplic_syscore_ops = {
+ .suspend = aplic_syscore_suspend,
+ .resume = aplic_syscore_resume,
+};
+
+static struct syscore aplic_syscore = {
+ .ops = &aplic_syscore_ops,
+};
+
+static int aplic_pm_notifier(struct notifier_block *nb, unsigned long action, void *data)
+{
+ struct aplic_priv *priv = container_of(nb, struct aplic_priv, genpd_nb);
+
+ switch (action) {
+ case GENPD_NOTIFY_PRE_OFF:
+ aplic_save_states(priv);
+ break;
+ case GENPD_NOTIFY_ON:
+ aplic_restore_states(priv);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static void aplic_pm_remove(void *data)
+{
+ struct aplic_priv *priv = data;
+ struct device *dev = priv->dev;
+
+ list_del(&priv->head);
+ if (dev->pm_domain)
+ dev_pm_genpd_remove_notifier(dev);
+}
+
+static int aplic_pm_add(struct device *dev, struct aplic_priv *priv)
+{
+ struct aplic_src_ctrl *srcs;
+ int ret;
+
+ srcs = devm_kzalloc(dev, (priv->nr_irqs + 1) * sizeof(*srcs), GFP_KERNEL);
+ if (!srcs)
+ return -ENOMEM;
+
+ priv->saved_hw_regs.srcs = srcs;
+ list_add(&priv->head, &aplics);
+ if (dev->pm_domain) {
+ priv->genpd_nb.notifier_call = aplic_pm_notifier;
+ ret = dev_pm_genpd_add_notifier(dev, &priv->genpd_nb);
+ if (ret)
+ goto remove_head;
+
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ goto remove_notifier;
+ }
+
+ return devm_add_action_or_reset(dev, aplic_pm_remove, priv);
+
+remove_notifier:
+ dev_pm_genpd_remove_notifier(dev);
+remove_head:
+ list_del(&priv->head);
+ return ret;
+}
+
void aplic_irq_unmask(struct irq_data *d)
{
struct aplic_priv *priv = irq_data_get_irq_chip_data(d);
@@ -60,6 +219,8 @@ int aplic_irq_set_type(struct irq_data *d, unsigned int type)
sourcecfg += (d->hwirq - 1) * sizeof(u32);
writel(val, sourcecfg);
+ priv->saved_hw_regs.srcs[d->hwirq - 1].sourcecfg = val;
+
return 0;
}
@@ -82,6 +243,7 @@ int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base,
void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode)
{
+ struct aplic_saved_regs *saved_regs = &priv->saved_hw_regs;
u32 val;
#ifdef CONFIG_RISCV_M_MODE
u32 valh;
@@ -95,6 +257,8 @@ void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode)
valh |= FIELD_PREP(APLIC_xMSICFGADDRH_HHXS, priv->msicfg.hhxs);
writel(val, priv->regs + APLIC_xMSICFGADDR);
writel(valh, priv->regs + APLIC_xMSICFGADDRH);
+ saved_regs->msiaddr = val;
+ saved_regs->msiaddrh = valh;
}
#endif
@@ -106,6 +270,8 @@ void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode)
writel(val, priv->regs + APLIC_DOMAINCFG);
if (readl(priv->regs + APLIC_DOMAINCFG) != val)
dev_warn(priv->dev, "unable to write 0x%x in domaincfg\n", val);
+
+ saved_regs->domaincfg = val;
}
static void aplic_init_hw_irqs(struct aplic_priv *priv)
@@ -176,7 +342,7 @@ int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, void __iomem *
/* Setup initial state APLIC interrupts */
aplic_init_hw_irqs(priv);
- return 0;
+ return aplic_pm_add(dev, priv);
}
static int aplic_probe(struct platform_device *pdev)
@@ -209,6 +375,8 @@ static int aplic_probe(struct platform_device *pdev)
if (rc)
dev_err_probe(dev, rc, "failed to setup APLIC in %s mode\n",
msi_mode ? "MSI" : "direct");
+ else
+ register_syscore(&aplic_syscore);
#ifdef CONFIG_ACPI
if (!acpi_disabled)
diff --git a/drivers/irqchip/irq-riscv-aplic-main.h b/drivers/irqchip/irq-riscv-aplic-main.h
index b0ad8cd..2d8ad71 100644
--- a/drivers/irqchip/irq-riscv-aplic-main.h
+++ b/drivers/irqchip/irq-riscv-aplic-main.h
@@ -23,7 +23,25 @@ struct aplic_msicfg {
u32 lhxw;
};
+struct aplic_src_ctrl {
+ u32 sourcecfg;
+ u32 target;
+ u32 ie;
+};
+
+struct aplic_saved_regs {
+ u32 domaincfg;
+#ifdef CONFIG_RISCV_M_MODE
+ u32 msiaddr;
+ u32 msiaddrh;
+#endif
+ struct aplic_src_ctrl *srcs;
+};
+
struct aplic_priv {
+ struct list_head head;
+ struct notifier_block genpd_nb;
+ struct aplic_saved_regs saved_hw_regs;
struct device *dev;
u32 gsi_base;
u32 nr_irqs;
@@ -40,6 +58,7 @@ int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base,
unsigned long *hwirq, unsigned int *type);
void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode);
int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, void __iomem *regs);
+void aplic_direct_restore_states(struct aplic_priv *priv);
int aplic_direct_setup(struct device *dev, void __iomem *regs);
#ifdef CONFIG_RISCV_APLIC_MSI
int aplic_msi_setup(struct device *dev, void __iomem *regs);
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 0/2] riscv-imsic/aplic: Preserve IMSIC and APLIC states during suspend
2025-12-02 6:07 [PATCH v3 0/2] riscv-imsic/aplic: Preserve IMSIC and APLIC states during suspend Nick Hu
2025-12-02 6:07 ` [PATCH v3 1/2] irqchip/riscv-imsic: Add a CPU pm notifier to restore the IMSIC on exit Nick Hu
2025-12-02 6:07 ` [PATCH v3 2/2] irqchip/riscv-aplic: Preserve APLIC states across suspend/resume Nick Hu
@ 2026-02-20 4:10 ` patchwork-bot+linux-riscv
2 siblings, 0 replies; 8+ messages in thread
From: patchwork-bot+linux-riscv @ 2026-02-20 4:10 UTC (permalink / raw)
To: Nick Hu
Cc: linux-riscv, anup, tglx, pjw, palmer, aou, alex, linux-kernel,
yongxuan.wang, cyan.yang, liujingqi
Hello:
This series was applied to riscv/linux.git (fixes)
by Thomas Gleixner <tglx@linutronix.de>:
On Tue, 02 Dec 2025 14:07:39 +0800 you wrote:
> Since the APLIC and IMSIC may be reset when the platform enters a deep
> sleep state, it is necessary to implement save and restore functions
> to ensure their states are correctly preserved and restored.
>
> Chagnes in V3:
> - Refine the commit messages and comments
> - Rename "imsic_restore()" to "imsic_hw_states_init()"
> - Rename "aplic_direct_restore()" to "aplic_direct_restore_states()"
> - Rename "aplic_add()" to "aplic_pm_add()"
> - Rename "aplic_remove()" to "aplic_pm_remove()"
> - Rename "aplic_save()" to "aplic_save_states()"
> - Rename "aplic_restore()" to "aplic_restore_states()"
> - Use "struct aplic_saved_regs" and "struct aplic_src_ctrl" to preserve
> the APLIC states
>
> [...]
Here is the summary with links:
- [v3,1/2] irqchip/riscv-imsic: Add a CPU pm notifier to restore the IMSIC on exit
https://git.kernel.org/riscv/c/f48b4bd0915b
- [v3,2/2] irqchip/riscv-aplic: Preserve APLIC states across suspend/resume
https://git.kernel.org/riscv/c/95a8ddde3660
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2026-02-20 4:10 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2025-12-02 6:07 [PATCH v3 0/2] riscv-imsic/aplic: Preserve IMSIC and APLIC states during suspend Nick Hu
2025-12-02 6:07 ` [PATCH v3 1/2] irqchip/riscv-imsic: Add a CPU pm notifier to restore the IMSIC on exit Nick Hu
2025-12-15 21:46 ` [tip: irq/drivers] " tip-bot2 for Nick Hu
2025-12-02 6:07 ` [PATCH v3 2/2] irqchip/riscv-aplic: Preserve APLIC states across suspend/resume Nick Hu
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2025-12-17 17:36 ` tip-bot2 for Nick Hu
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