* [PATCH v5 1/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0
2026-03-17 7:37 [PATCH v5 0/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch nodes Sushrut Shree Trivedi
@ 2026-03-17 7:37 ` Sushrut Shree Trivedi
2026-03-17 7:37 ` [PATCH v5 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1 Sushrut Shree Trivedi
2026-03-19 3:31 ` [PATCH v5 0/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch nodes Bjorn Andersson
2 siblings, 0 replies; 4+ messages in thread
From: Sushrut Shree Trivedi @ 2026-03-17 7:37 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Dmitry Baryshkov,
Sushrut Shree Trivedi, Konrad Dybcio
Add a node for the TC9563 PCIe switch connected to PCIe0. The switch
has three downstream ports.Two embedded Ethernet devices are present
on one of the downstream ports. The other downstream ports route to
M.2 E key and PCIe x4 connector respectively. All the ports present
in the node represent the downstream ports and embedded endpoints.
Power to the TC9563 is supplied through two LDO regulators, which
are on by default and are added as fixed regulators. TC9563 can be
configured through I2C.
Since PCIe0 now routes to TC9563 instead of WCN6750, disable the
WCN6750 and WPSS device tree nodes to reflect the actual hardware
configuration and avoid probing issues.
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
.../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 167 +++++++++++++++++++++
1 file changed, 167 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
index 619a42b5ef48..ad2795668ec8 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
@@ -5,9 +5,37 @@
/dts-v1/;
/plugin/;
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+&{/} {
+
+ vreg_0p9: regulator-0v9 {
+ compatible = "regulator-fixed";
+ regulator-name = "VREG_0P9";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vreg_1p8: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VREG_1P8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&remoteproc_wpss {
+ status = "disabled";
+};
+
&spi11 {
#address-cells = <1>;
#size-cells = <0>;
@@ -19,3 +47,142 @@ st33htpm0: tpm@0 {
spi-max-frequency = <20000000>;
};
};
+
+&pcie0 {
+ perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>;
+ pinctrl-names = "default";
+
+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
+ <0x100 &apps_smmu 0x1c01 0x1>,
+ <0x208 &apps_smmu 0x1c04 0x1>,
+ <0x210 &apps_smmu 0x1c05 0x1>,
+ <0x218 &apps_smmu 0x1c06 0x1>,
+ <0x300 &apps_smmu 0x1c07 0x1>,
+ <0x400 &apps_smmu 0x1c08 0x1>,
+ <0x500 &apps_smmu 0x1c09 0x1>,
+ <0x501 &apps_smmu 0x1c10 0x1>;
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l10c_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+
+ status = "okay";
+};
+
+&pcie0_port {
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ pcie@0,0 {
+ compatible = "pci1179,0623";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x2 0xff>;
+
+ vddc-supply = <&vreg_0p9>;
+ vdd18-supply = <&vreg_1p8>;
+ vdd09-supply = <&vreg_0p9>;
+ vddio1-supply = <&vreg_1p8>;
+ vddio2-supply = <&vreg_1p8>;
+ vddio18-supply = <&vreg_1p8>;
+
+ i2c-parent = <&i2c1 0x33>;
+
+ resx-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie0_tc9563_resx_n>;
+ pinctrl-names = "default";
+
+ pcie@1,0 {
+ reg = <0x20800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x3 0xff>;
+ };
+
+ pcie@2,0 {
+ reg = <0x21000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x4 0xff>;
+ };
+
+ pcie@3,0 {
+ reg = <0x21800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ bus-range = <0x5 0xff>;
+
+ pci@0,0 {
+ reg = <0x50000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+
+ pci@0,1 {
+ reg = <0x50100 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+ };
+
+ };
+};
+
+&tlmm {
+ pcie0_tc9563_resx_n: pcie0-tc9563-resx-state {
+ pins = "gpio78";
+ function = "gpio";
+ bias-disable;
+ input-disable;
+ output-enable;
+ };
+
+ pcie0_reset_n: pcie0-reset-n-state {
+ pins = "gpio87";
+ function = "gpio";
+ drive-strength = <16>;
+ output-low;
+ bias-disable;
+ };
+
+ pcie0_clkreq_n: pcie0-clkreq-n-state {
+ pins = "gpio88";
+ function = "pcie0_clkreqn";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ pcie0_wake_n: pcie0-wake-n-state {
+ pins = "gpio89";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+};
+
+&wifi {
+ status = "disabled";
+};
--
2.25.1
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH v5 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1
2026-03-17 7:37 [PATCH v5 0/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch nodes Sushrut Shree Trivedi
2026-03-17 7:37 ` [PATCH v5 1/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0 Sushrut Shree Trivedi
@ 2026-03-17 7:37 ` Sushrut Shree Trivedi
2026-03-19 3:31 ` [PATCH v5 0/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch nodes Bjorn Andersson
2 siblings, 0 replies; 4+ messages in thread
From: Sushrut Shree Trivedi @ 2026-03-17 7:37 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Dmitry Baryshkov,
Sushrut Shree Trivedi, Konrad Dybcio
Add a node for the second TC9563 PCIe switch on PCIe1, which is connected
in cascade to the first TC9563 switch via the former's downstream port.
Two embedded Ethernet devices are present on one of the downstream
ports of this second switch as well. All the ports present in the
node represent the downstream ports and embedded endpoints.
The second TC9563 is powered up via the same LDO regulators as the first
one, and these can be controlled via two GPIOs, which are already present
as fixed regulators. This TC9563 can also be configured through I2C.
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
.../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 102 +++++++++++++++++++++
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 2 +-
2 files changed, 103 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
index ad2795668ec8..83908db335af 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
@@ -150,6 +150,100 @@ pci@0,1 {
};
};
+&pcie1 {
+ iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
+ <0x100 &apps_smmu 0x1c81 0x1>,
+ <0x208 &apps_smmu 0x1c84 0x1>,
+ <0x210 &apps_smmu 0x1c85 0x1>,
+ <0x218 &apps_smmu 0x1c86 0x1>,
+ <0x300 &apps_smmu 0x1c87 0x1>,
+ <0x408 &apps_smmu 0x1c90 0x1>,
+ <0x410 &apps_smmu 0x1c91 0x1>,
+ <0x418 &apps_smmu 0x1c92 0x1>,
+ <0x500 &apps_smmu 0x1c93 0x1>,
+ <0x600 &apps_smmu 0x1c94 0x1>,
+ <0x700 &apps_smmu 0x1c95 0x1>,
+ <0x701 &apps_smmu 0x1c96 0x1>,
+ <0x800 &apps_smmu 0x1c97 0x1>,
+ <0x900 &apps_smmu 0x1c98 0x1>,
+ <0x901 &apps_smmu 0x1c99 0x1>;
+};
+
+&pcie1_switch0_dsp1 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ pcie@0,0 {
+ compatible = "pci1179,0623";
+ reg = <0x30000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x2 0xff>;
+
+ vddc-supply = <&vdd_ntn_0p9>;
+ vdd18-supply = <&vdd_ntn_1p8>;
+ vdd09-supply = <&vdd_ntn_0p9>;
+ vddio1-supply = <&vdd_ntn_1p8>;
+ vddio2-supply = <&vdd_ntn_1p8>;
+ vddio18-supply = <&vdd_ntn_1p8>;
+
+ i2c-parent = <&i2c1 0x77>;
+
+ resx-gpios = <&tlmm 124 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie1_tc9563_resx_n>;
+ pinctrl-names = "default";
+
+ pcie@1,0 {
+ reg = <0x40800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x3 0xff>;
+ };
+
+ pcie@2,0 {
+ reg = <0x41000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x4 0xff>;
+ };
+
+ pcie@3,0 {
+ reg = <0x41800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ bus-range = <0x5 0xff>;
+
+ pci@0,0 {
+ reg = <0x50000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+
+ pci@0,1 {
+ reg = <0x50100 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+ };
+ };
+};
+
&tlmm {
pcie0_tc9563_resx_n: pcie0-tc9563-resx-state {
pins = "gpio78";
@@ -181,6 +275,14 @@ pcie0_wake_n: pcie0-wake-n-state {
bias-pull-up;
};
+ pcie1_tc9563_resx_n: pcie1-tc9563-resx-state {
+ pins = "gpio124";
+ function = "gpio";
+ bias-disable;
+ input-disable;
+ output-enable;
+ };
+
};
&wifi {
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index e3d2f01881ae..cd54525e45e0 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -852,7 +852,7 @@ pcie@0,0 {
pinctrl-0 = <&tc9563_resx_n>;
pinctrl-names = "default";
- pcie@1,0 {
+ pcie1_switch0_dsp1: pcie@1,0 {
reg = <0x20800 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
--
2.25.1
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v5 0/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch nodes
2026-03-17 7:37 [PATCH v5 0/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch nodes Sushrut Shree Trivedi
2026-03-17 7:37 ` [PATCH v5 1/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0 Sushrut Shree Trivedi
2026-03-17 7:37 ` [PATCH v5 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1 Sushrut Shree Trivedi
@ 2026-03-19 3:31 ` Bjorn Andersson
2 siblings, 0 replies; 4+ messages in thread
From: Bjorn Andersson @ 2026-03-19 3:31 UTC (permalink / raw)
To: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Sushrut Shree Trivedi
Cc: linux-arm-msm, devicetree, linux-kernel, Dmitry Baryshkov, Konrad Dybcio
On Tue, 17 Mar 2026 13:07:06 +0530, Sushrut Shree Trivedi wrote:
> Add nodes for the two additional TC9563 PCIe switches present on the
> QCOM RB3Gen2 Industrial Mezzanine platform.
>
> One of the TC9563 is connected directly to the PCIe0 root-port while
> the second TC9563 switch is connected in cascade fashion to another
> already available TC9563 switch on PCIe1 via the former's downstream
> port (DSP). The final PCIe hierarchy on the Industrial Mezz platform
> would look something like below:
>
> [...]
Applied, thanks!
[1/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0
commit: 07a6bd7de086640838eb4b46aaf1c440bcd01d5a
[2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1
commit: bdb33e4f15172d42d84b6b3bf90893dafbbfebcf
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 4+ messages in thread