[PATCH v3 1/1] reset: imx7: Correct polarity of MIPI CSI resets on i.MX8MQ

[PATCH v3 1/1] reset: imx7: Correct polarity of MIPI CSI resets on i.MX8MQ

[robby.cai]

From: Robby Cai <robby.cai@nxp.com>

On i.MX8MQ, the MIPI CSI reset lines are active-low and not self-clearing.
Writing '0' asserts reset and it remains asserted until explicitly
deasserted by software.

This driver previously treated the MIPI CSI reset signals as active-high,
which led to incorrect reset assert/deassert sequencing. This issue was
exposed by commit 6d79bb8fd2aa ("media: imx8mq-mipi-csi2: Explicitly
release reset").

Fix this by reflecting the correct reset polarity and ensuring proper
reset handling.

Fixes: c979dbf59987 ("reset: imx7: Add support for i.MX8MQ IP block variant")
Cc: <stable@vger.kernel.org> # 6d79bb8fd2aa: media: imx8mq-mipi-csi2: Explicitly release reset
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Robby Cai <robby.cai@nxp.com>

---

Changes in v3:
 - Add Cc tag as suggested by Philipp Zabel
 - Add R-b tag from Philipp Zabel

Link to v2: https://lore.kernel.org/imx/20260417080851.489303-1-robby.cai@nxp.com/

Changes in v2:
 - Drop the naming change in response to feedback from Krzysztof Kozlowski
 - Refine the patch subject and commit message

Link to v1: https://lore.kernel.org/imx/20260331101331.1405588-1-robby.cai@nxp.com/

---
 drivers/reset/reset-imx7.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index dd01fe11c5cb..a3cb8244d76a 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -236,6 +236,12 @@ static int imx8mq_reset_set(struct reset_controller_dev *rcdev,
 
 	case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
 	case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN:
+	case IMX8MQ_RESET_MIPI_CSI1_CORE_RESET:
+	case IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET:
+	case IMX8MQ_RESET_MIPI_CSI1_ESC_RESET:
+	case IMX8MQ_RESET_MIPI_CSI2_CORE_RESET:
+	case IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET:
+	case IMX8MQ_RESET_MIPI_CSI2_ESC_RESET:
 	case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N:
 	case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N:
 	case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N:
-- 
2.50.1

Re: [PATCH v3 1/1] reset: imx7: Correct polarity of MIPI CSI resets on i.MX8MQ

[Frank Li]

On Fri, Jun 19, 2026 at 03:31:15PM +0800, robby.cai@oss.nxp.com wrote:
> [You don't often get email from robby.cai@oss.nxp.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> From: Robby Cai <robby.cai@nxp.com>
>
> On i.MX8MQ, the MIPI CSI reset lines are active-low and not self-clearing.
> Writing '0' asserts reset and it remains asserted until explicitly
> deasserted by software.
>
> This driver previously treated the MIPI CSI reset signals as active-high,
> which led to incorrect reset assert/deassert sequencing. This issue was
> exposed by commit 6d79bb8fd2aa ("media: imx8mq-mipi-csi2: Explicitly
> release reset").
>
> Fix this by reflecting the correct reset polarity and ensuring proper
> reset handling.
>
> Fixes: c979dbf59987 ("reset: imx7: Add support for i.MX8MQ IP block variant")
> Cc: <stable@vger.kernel.org> # 6d79bb8fd2aa: media: imx8mq-mipi-csi2: Explicitly release reset
> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
> Signed-off-by: Robby Cai <robby.cai@nxp.com>

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>
> ---
>
> Changes in v3:
>  - Add Cc tag as suggested by Philipp Zabel
>  - Add R-b tag from Philipp Zabel
>
> Link to v2: https://lore.kernel.org/imx/20260417080851.489303-1-robby.cai@nxp.com/
>
> Changes in v2:
>  - Drop the naming change in response to feedback from Krzysztof Kozlowski
>  - Refine the patch subject and commit message
>
> Link to v1: https://lore.kernel.org/imx/20260331101331.1405588-1-robby.cai@nxp.com/
>
> ---
>  drivers/reset/reset-imx7.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
> index dd01fe11c5cb..a3cb8244d76a 100644
> --- a/drivers/reset/reset-imx7.c
> +++ b/drivers/reset/reset-imx7.c
> @@ -236,6 +236,12 @@ static int imx8mq_reset_set(struct reset_controller_dev *rcdev,
>
>         case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
>         case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN:
> +       case IMX8MQ_RESET_MIPI_CSI1_CORE_RESET:
> +       case IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET:
> +       case IMX8MQ_RESET_MIPI_CSI1_ESC_RESET:
> +       case IMX8MQ_RESET_MIPI_CSI2_CORE_RESET:
> +       case IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET:
> +       case IMX8MQ_RESET_MIPI_CSI2_ESC_RESET:
>         case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N:
>         case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N:
>         case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N:
> --
> 2.50.1
>
>

Re: [PATCH v3 1/1] reset: imx7: Correct polarity of MIPI CSI resets on i.MX8MQ

[guoniu.zhou]

On Fri, 19 Jun 2026 15:31:15 +0800, robby.cai@oss.nxp.com <robby.cai@oss.nxp.com> wrote:
> reset: imx7: Correct polarity of MIPI CSI resets on i.MX8MQ

Reviewed-by: Guoniu Zhou <guoniu.zhou@oss.nxp.com>

-- 
Guoniu Zhou <guoniu.zhou@oss.nxp.com>

Re: [PATCH v3 1/1] reset: imx7: Correct polarity of MIPI CSI resets on i.MX8MQ

[Philipp Zabel]

On Fr, 2026-06-19 at 15:31 +0800, robby.cai@oss.nxp.com wrote:
> From: Robby Cai <robby.cai@nxp.com>
> 
> On i.MX8MQ, the MIPI CSI reset lines are active-low and not self-clearing.
> Writing '0' asserts reset and it remains asserted until explicitly
> deasserted by software.
> 
> This driver previously treated the MIPI CSI reset signals as active-high,
> which led to incorrect reset assert/deassert sequencing. This issue was
> exposed by commit 6d79bb8fd2aa ("media: imx8mq-mipi-csi2: Explicitly
> release reset").
> 
> Fix this by reflecting the correct reset polarity and ensuring proper
> reset handling.
[...]

Applied to reset/fixes, thanks!

[1/1] reset: imx7: Correct polarity of MIPI CSI resets on i.MX8MQ
      https://git.kernel.org/pub/scm/linux/kernel/git/pza/linux.git/commit/?id=71827776667f

regards
Philipp