Re: (subset) [PATCH v2 0/5] Add CMN PLL clock controller support for IPQ5332

[Bjorn Andersson <andersson@kernel.org>]

On Tue, 06 Jan 2026 21:35:09 -0800, Luo Jie wrote:
> This patch series adds support for the CMN PLL block on the IPQ5332 SoC.
> The CMN PLL implementation in IPQ5332 is largely similar to that of
> IPQ9574, which is already supported by the driver. The primary difference
> is that the fixed output clocks to PPE from the CMN PLL operate at 200 MHz.
> 
> Additionally, IPQ5332 provides a single 50 MHz clock to both UNIPHY (PCS)
> instances, which in turn supply either 25 MHz or 50 MHz to the connected
> Ethernet PHY or switch.
> 
> [...]

Applied, thanks!

[4/5] arm64: dts: ipq5332: Add CMN PLL node for networking hardware
      commit: eba1bea1123924f8bf187ad175d1667036f34e80
[5/5] arm64: dts: qcom: Represent xo_board as fixed-factor clock on IPQ5332
      commit: 985650336dcfe8fa640196a49956c5983dfe2696

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>