From: Bjorn Andersson <andersson@kernel.org>
To: Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Subject: Re: [PATCH] arm64: dts: qcom: eliza: Fix DSI1 phy reference clock rate
Date: Wed, 29 Jul 2026 20:55:39 -0500 [thread overview]
Message-ID: <178537653467.67965.5833816759757321877.b4-ty@kernel.org> (raw)
In-Reply-To: <20260713125837.727632-2-krzysztof.kozlowski@oss.qualcomm.com>
On Mon, 13 Jul 2026 14:58:38 +0200, Krzysztof Kozlowski wrote:
> The DSI PHY CXO clock input is the SoC CXO divided by two. DSI0 already
> uses correct one, but DSI1 got copy-paste from SM8750, which had same
> problem and copy-pasted code from SM8650. Wrong clock parent will cause
> incorrect DSI1 PHY PLL frequencies to be used making the DSI panel
> non-working, although there is no upstream user of DSI1.
>
>
> [...]
Applied, thanks!
[1/1] arm64: dts: qcom: eliza: Fix DSI1 phy reference clock rate
commit: a3ba349af8e1bb7e0efdcd2dd53d69282f18478a
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
prev parent reply other threads:[~2026-07-30 1:55 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-13 12:58 Krzysztof Kozlowski
2026-07-14 7:13 ` Konrad Dybcio
2026-07-30 1:55 ` Bjorn Andersson [this message]
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