* [PATCH] arm64: dts: qcom: eliza: Fix DSI1 phy reference clock rate
@ 2026-07-13 12:58 Krzysztof Kozlowski
2026-07-14 7:13 ` Konrad Dybcio
2026-07-30 1:55 ` Bjorn Andersson
0 siblings, 2 replies; 3+ messages in thread
From: Krzysztof Kozlowski @ 2026-07-13 12:58 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, linux-arm-msm, devicetree,
linux-kernel
Cc: Krzysztof Kozlowski
The DSI PHY CXO clock input is the SoC CXO divided by two. DSI0 already
uses correct one, but DSI1 got copy-paste from SM8750, which had same
problem and copy-pasted code from SM8650. Wrong clock parent will cause
incorrect DSI1 PHY PLL frequencies to be used making the DSI panel
non-working, although there is no upstream user of DSI1.
Fixes: 159d252ed800 ("arm64: dts: qcom: eliza: Add display (MDSS) with Display CC")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
Fix for current RC
---
arch/arm64/boot/dts/qcom/eliza.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi
index 357e8066c176..ecda1f448a1b 100644
--- a/arch/arm64/boot/dts/qcom/eliza.dtsi
+++ b/arch/arm64/boot/dts/qcom/eliza.dtsi
@@ -2557,7 +2557,7 @@ mdss_dsi1_phy: phy@ae97000 {
"dsi_pll";
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
- <&rpmhcc RPMH_CXO_CLK>;
+ <&bi_tcxo_div2>;
clock-names = "iface",
"ref";
--
2.53.0
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] arm64: dts: qcom: eliza: Fix DSI1 phy reference clock rate
2026-07-13 12:58 [PATCH] arm64: dts: qcom: eliza: Fix DSI1 phy reference clock rate Krzysztof Kozlowski
@ 2026-07-14 7:13 ` Konrad Dybcio
2026-07-30 1:55 ` Bjorn Andersson
1 sibling, 0 replies; 3+ messages in thread
From: Konrad Dybcio @ 2026-07-14 7:13 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Dmitry Baryshkov,
linux-arm-msm, devicetree, linux-kernel
On 7/13/26 2:58 PM, Krzysztof Kozlowski wrote:
> The DSI PHY CXO clock input is the SoC CXO divided by two. DSI0 already
> uses correct one, but DSI1 got copy-paste from SM8750, which had same
> problem and copy-pasted code from SM8650. Wrong clock parent will cause
> incorrect DSI1 PHY PLL frequencies to be used making the DSI panel
> non-working, although there is no upstream user of DSI1.
>
> Fixes: 159d252ed800 ("arm64: dts: qcom: eliza: Add display (MDSS) with Display CC")
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] arm64: dts: qcom: eliza: Fix DSI1 phy reference clock rate
2026-07-13 12:58 [PATCH] arm64: dts: qcom: eliza: Fix DSI1 phy reference clock rate Krzysztof Kozlowski
2026-07-14 7:13 ` Konrad Dybcio
@ 2026-07-30 1:55 ` Bjorn Andersson
1 sibling, 0 replies; 3+ messages in thread
From: Bjorn Andersson @ 2026-07-30 1:55 UTC (permalink / raw)
To: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Dmitry Baryshkov, linux-arm-msm, devicetree, linux-kernel,
Krzysztof Kozlowski
On Mon, 13 Jul 2026 14:58:38 +0200, Krzysztof Kozlowski wrote:
> The DSI PHY CXO clock input is the SoC CXO divided by two. DSI0 already
> uses correct one, but DSI1 got copy-paste from SM8750, which had same
> problem and copy-pasted code from SM8650. Wrong clock parent will cause
> incorrect DSI1 PHY PLL frequencies to be used making the DSI panel
> non-working, although there is no upstream user of DSI1.
>
>
> [...]
Applied, thanks!
[1/1] arm64: dts: qcom: eliza: Fix DSI1 phy reference clock rate
commit: a3ba349af8e1bb7e0efdcd2dd53d69282f18478a
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2026-07-13 12:58 [PATCH] arm64: dts: qcom: eliza: Fix DSI1 phy reference clock rate Krzysztof Kozlowski
2026-07-14 7:13 ` Konrad Dybcio
2026-07-30 1:55 ` Bjorn Andersson
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