From: Oleg Keri <okerixx@gmail.com>
To: Rob Clark <rob.clark@oss.qualcomm.com>,
Thorsten Leemhuis <regressions@leemhuis.info>
Cc: Bjorn Andersson <andersson@kernel.org>,
Akhil P Oommen <akhilpo@oss.qualcomm.com>,
Sean Paul <sean@poorly.run>,
Konrad Dybcio <konradybcio@kernel.org>,
Dmitry Baryshkov <lumag@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Jessica Zhang <jesszhan0024@gmail.com>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
regressions@lists.linux.dev
Subject: Re: [PATCH 3/3] drm/msm/a8xx: Enable CLX feature on Adreno X2-85
Date: Tue, 20 Oct 2026 10:57:18 +0200 [thread overview]
Message-ID: <179248663855.32151.9955864156939592299@gmail.com> (raw)
In-Reply-To: <CACSVV00x091i7BKW+bj0RUnkd4rOrHXbhZ4zF6SuTU1NAqsFTA@mail.gmail.com>
I guess this should be investigated further. Yoga Slim 7x Gen 11, no modules,
firmware built in, so the GMU comes up at 0.6 s.
It's rpmhpd. Before its sync_state, rpmhpd_aggregate_corner() pushes every
vote to the highest corner. The gxclkctl probe does a runtime resume/suspend
of its GFX and GMXC domains at 0.18 s (qcom_cc_probe -> pm_runtime -> genpd
-> rpmhpd_power_on), and from that point both rails are stuck at max until
rpmhpd syncs, which is at 2.8 s here. The GMU then does its CLX DCVS
calibration on a rail that won't move.
The GMU log buffer (fw v5.2.38) agrees: the calibration trace of the bad
boot matches the first good one step for step up to the ninth level. There
it stops, and the firmware puts HFI_F2H_MSG_ERROR 0x007306c7
"ResMgrCalibrateDcvsLvl" on the debug queue. The GX_BW_PERF_VOTE timeout is
simply the next message we send.
With gfx and gmxc taken out of the clamp (hack below) the first GPU init at
0.6 s just works, CLX tables included. Three boots so far.
The wedged GMU after a failed attempt is a different story. Retries after
rpmhpd's sync_state still die with "GMU firmware initialization timed out"
until gpucc's sync_state (fw_devlink timeout, 13 s) collapses CX. That's
what the gpu_cc_cx_gdsc/NO_STAY_ON thing in my earlier mail was about: the
recovery, not the cause.
The RSC side is not it. On A8xx the GMU firmware loads the RSC sequencer
code and TCS slots on its own; preloading them before the first boot made
no difference.
Abel's CRD failing even with msm loaded at 90 s doesn't match this, unless
something keeps gfx.lvl high on the CRD after sync_state. Could be a second
problem.
--- a/drivers/pmdomain/qcom/rpmhpd.c
+++ b/drivers/pmdomain/qcom/rpmhpd.c
@@ -1009,7 +1009,7 @@ static int rpmhpd_aggregate_corner(struct rpmhpd *pd, unsigned int corner)
- if (pd->state_synced) {
+ if (pd->state_synced || pd == &gfx || pd == &gmxc) {
to_active_sleep(pd, corner, &this_active_corner, &this_sleep_corner);
} else {
/* Clamp to highest corner if sync_state hasn't happened */
Oleg
next prev parent reply other threads:[~2026-10-20 8:57 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-15 20:07 [PATCH 0/3] drm/msm/adreno: Support for CLX feature on A8xx Akhil P Oommen
2026-05-15 20:07 ` [PATCH 1/3] drm/msm/a6xx: Add HFI support for CLX feature Akhil P Oommen
2026-05-18 8:04 ` Konrad Dybcio
2026-05-18 8:05 ` Konrad Dybcio
2026-05-15 20:07 ` [PATCH 2/3] drm/msm/a6xx: Enable CLX feature on A840 Akhil P Oommen
2026-05-18 8:10 ` Konrad Dybcio
2026-05-15 20:07 ` [PATCH 3/3] drm/msm/a8xx: Enable CLX feature on Adreno X2-85 Akhil P Oommen
2026-05-18 8:11 ` Konrad Dybcio
2026-10-02 14:38 ` Bjorn Andersson
2026-10-02 17:47 ` Oleg Keri
2026-10-02 18:12 ` Rob Clark
2026-10-02 18:29 ` Oleg Keri
2026-10-02 18:43 ` Rob Clark
2026-10-19 13:43 ` Thorsten Leemhuis
2026-10-19 15:53 ` Rob Clark
2026-10-20 8:57 ` Oleg Keri [this message]
2026-10-21 5:49 ` Akhil P Oommen
2026-10-02 21:51 ` Akhil P Oommen
2026-10-03 19:13 ` Oleg Keri
2026-10-19 20:32 ` Abel Vesa
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