Re: [PATCH 2/3] drm/msm/a6xx: Enable CLX feature on A840

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 5/15/26 10:07 PM, Akhil P Oommen wrote:
> Add the A840 CLX domain table and the IFF/PCLX limits table to the
> catalog. With the HFI plumbing in place, this enables the Current Limit
> Extension (CLX) feature on Adreno 840.
> 
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 86 +++++++++++++++++++++++++++++++
>  1 file changed, 86 insertions(+)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index 550ff3a9b82e..c503912a61c7 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -2108,6 +2108,90 @@ static const struct adreno_reglist_pipe a840_dyn_pwrup_reglist_regs[] = {
>  };
>  DECLARE_ADRENO_REGLIST_PIPE_LIST(a840_dyn_pwrup_reglist);
>  
> +static const struct a6xx_hfi_clx_table_v2_cmd a840_clx_tbl = {
> +	.version = (2 << 16) | 1,

Is that major/minor or major=2 minor=0 patch=1? Please add a define

otherwise

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad