* [PATCH v10 1/3] dt-bindings: phy: aspeed: Add ASPEED PCIe PHY
2026-10-20 11:59 [PATCH v10 0/3] Add ASPEED PCIe PHY support Jacky Chou
@ 2026-10-20 11:59 ` Jacky Chou
2026-10-20 16:29 ` Rob Herring (Arm)
2026-10-20 11:59 ` [PATCH v10 2/3] phy: aspeed: Add ASPEED PCIe PHY driver Jacky Chou
2026-10-20 11:59 ` [PATCH v10 3/3] MAINTAINERS: " Jacky Chou
2 siblings, 1 reply; 5+ messages in thread
From: Jacky Chou @ 2026-10-20 11:59 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery,
Ryan Chen, Billy Tsai
Cc: linux-aspeed, linux-phy, devicetree, linux-arm-kernel,
linux-kernel, Jacky Chou
Introduce device-binding for ASPEED AST2600/2700 PCIe PHY.
The PHY provides the physical layer used by the PCIe
controller when operating in root complex mode.
Describe the compatible strings, register range, clocks and
phy-cells value required by the PHY provider.
Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
---
.../bindings/phy/aspeed,ast2600-pcie-phy.yaml | 49 ++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml
new file mode 100644
index 000000000000..686b2e3d9457
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/aspeed,ast2600-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED PCIe PHY
+
+maintainers:
+ - Jacky Chou <jacky_chou@aspeedtech.com>
+
+description:
+ The ASPEED PCIe PHY provides the physical layer functionality for PCIe
+ controllers in the SoC.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - aspeed,ast2600-pcie-phy
+ - aspeed,ast2700-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description:
+ Fixed 100MHz reference clock provided on the board.
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@1e6ed200 {
+ compatible = "aspeed,ast2600-pcie-phy";
+ reg = <0x1e6ed200 0x100>;
+ clocks = <&pcie_refclk>;
+ #phy-cells = <0>;
+ };
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v10 2/3] phy: aspeed: Add ASPEED PCIe PHY driver
2026-10-20 11:59 [PATCH v10 0/3] Add ASPEED PCIe PHY support Jacky Chou
2026-10-20 11:59 ` [PATCH v10 1/3] dt-bindings: phy: aspeed: Add ASPEED PCIe PHY Jacky Chou
@ 2026-10-20 11:59 ` Jacky Chou
2026-10-20 11:59 ` [PATCH v10 3/3] MAINTAINERS: " Jacky Chou
2 siblings, 0 replies; 5+ messages in thread
From: Jacky Chou @ 2026-10-20 11:59 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery,
Ryan Chen, Billy Tsai
Cc: linux-aspeed, linux-phy, devicetree, linux-arm-kernel,
linux-kernel, Jacky Chou
Introduce support for Aspeed PCIe PHY controller available in
AST2600/2700.
Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
---
drivers/phy/aspeed/Kconfig | 12 +-
drivers/phy/aspeed/Makefile | 1 +
drivers/phy/aspeed/phy-aspeed-pcie.c | 230 +++++++++++++++++++++++++++++++++++
3 files changed, 242 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/aspeed/Kconfig b/drivers/phy/aspeed/Kconfig
index 7b5f48db2be8..b5903cf06268 100644
--- a/drivers/phy/aspeed/Kconfig
+++ b/drivers/phy/aspeed/Kconfig
@@ -1,9 +1,19 @@
# SPDX-License-Identifier: GPL-2.0-only
-
#
# PHY drivers for ASPEED
#
+config PHY_ASPEED_PCIE
+ tristate "ASPEED PCIe PHY driver"
+ select GENERIC_PHY
+ depends on (ARCH_ASPEED || COMPILE_TEST)
+ help
+ This option enables support for the ASPEED PCIe PHY driver.
+ The driver provides the necessary interface to control and
+ configure the PCIe PHY hardware found on ASPEED SoCs.
+ It is required for proper operation of PCIe devices on
+ platforms using ASPEED chips.
+
config PHY_ASPEED_USB3
tristate "ASPEED USB3 PHY driver"
select GENERIC_PHY
diff --git a/drivers/phy/aspeed/Makefile b/drivers/phy/aspeed/Makefile
index d96d9d73a009..9d43790fdda8 100644
--- a/drivers/phy/aspeed/Makefile
+++ b/drivers/phy/aspeed/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_PHY_ASPEED_PCIE) += phy-aspeed-pcie.o
obj-$(CONFIG_PHY_ASPEED_USB3) += phy-aspeed-usb3.o
diff --git a/drivers/phy/aspeed/phy-aspeed-pcie.c b/drivers/phy/aspeed/phy-aspeed-pcie.c
new file mode 100644
index 000000000000..0a18c0eb35cf
--- /dev/null
+++ b/drivers/phy/aspeed/phy-aspeed-pcie.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 Aspeed Technology Inc.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/phy/pcie.h>
+#include <linux/phy/phy.h>
+
+/* AST2600 PCIe Host Controller Registers */
+#define PEHR_GLOBAL 0x30
+#define AST2600_PORT_TYPE_MASK GENMASK(5, 4)
+#define PEHR_LOCK 0x7c
+#define PCIE_UNLOCK 0xa8
+
+/* AST2700 PEHR */
+#define PEHR_MISC_58 0x58
+#define LOCAL_SCALE_SUP BIT(0)
+#define PEHR_MISC_5C 0x5c
+#define CONFIG_RC_DEVICE BIT(30)
+#define PEHR_MISC_60 0x60
+#define AST2700_PORT_TYPE_MASK GENMASK(7, 4)
+#define PORT_TYPE_ROOT 0x4
+#define PEHR_MISC_70 0x70
+#define POSTED_DATA_CREDITS(x) FIELD_PREP(GENMASK(15, 0), x)
+#define POSTED_HEADER_CREDITS(x) FIELD_PREP(GENMASK(27, 16), x)
+#define PEHR_MISC_78 0x78
+#define COMPLETION_DATA_CREDITS(x) FIELD_PREP(GENMASK(15, 0), x)
+#define COMPLETION_HEADER_CREDITS(x) FIELD_PREP(GENMASK(27, 16), x)
+#define PEHR_MISC_278 0x278
+#define SET_TO_DOWNSTREAM BIT(22)
+#define ASSERT_INTERNAL_RESET BIT(31)
+#define PEHR_MISC_280 0x280
+#define SEL_INTERNAL_RESET BIT(0)
+
+/**
+ * struct aspeed_pcie_phy - PCIe PHY information
+ * @reg: PCIe host register base address
+ * @clk: PCIe reference clock
+ * @phy: pointer to PHY structure
+ * @platform: platform specific information
+ */
+struct aspeed_pcie_phy {
+ void __iomem *reg;
+ struct clk *clk;
+ struct phy *phy;
+ const struct aspeed_pcie_phy_platform *platform;
+};
+
+/**
+ * struct aspeed_pcie_phy_platform - Platform information
+ * @phy_ops: phy operations
+ */
+struct aspeed_pcie_phy_platform {
+ const struct phy_ops *phy_ops;
+};
+
+static int ast2600_phy_init(struct phy *phy)
+{
+ struct aspeed_pcie_phy *pcie_phy = phy_get_drvdata(phy);
+ int ret;
+
+ ret = clk_prepare_enable(pcie_phy->clk);
+ if (ret)
+ return ret;
+
+ writel(PCIE_UNLOCK, pcie_phy->reg + PEHR_LOCK);
+
+ return 0;
+}
+
+static int aspeed_pcie_phy_exit(struct phy *phy)
+{
+ struct aspeed_pcie_phy *pcie_phy = phy_get_drvdata(phy);
+
+ clk_disable_unprepare(pcie_phy->clk);
+
+ return 0;
+}
+
+static int ast2600_phy_set_mode(struct phy *phy, enum phy_mode mode,
+ int submode)
+{
+ struct aspeed_pcie_phy *pcie_phy = phy_get_drvdata(phy);
+ u32 cfg_val;
+
+ switch (submode) {
+ case PHY_MODE_PCIE_RC:
+ cfg_val = readl(pcie_phy->reg + PEHR_GLOBAL);
+ FIELD_MODIFY(AST2600_PORT_TYPE_MASK, &cfg_val, 0x3);
+ writel(cfg_val, pcie_phy->reg + PEHR_GLOBAL);
+ break;
+ default:
+ dev_err(&phy->dev, "Unsupported submode %d\n", submode);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct phy_ops ast2600_phy_ops = {
+ .init = ast2600_phy_init,
+ .exit = aspeed_pcie_phy_exit,
+ .set_mode = ast2600_phy_set_mode,
+ .owner = THIS_MODULE,
+};
+
+static int ast2700_phy_init(struct phy *phy)
+{
+ struct aspeed_pcie_phy *pcie_phy = phy_get_drvdata(phy);
+
+ return clk_prepare_enable(pcie_phy->clk);
+}
+
+static int ast2700_phy_set_mode(struct phy *phy, enum phy_mode mode,
+ int submode)
+{
+ struct aspeed_pcie_phy *pcie_phy = phy_get_drvdata(phy);
+ u32 cfg_val;
+
+ switch (submode) {
+ case PHY_MODE_PCIE_RC:
+ writel(0, pcie_phy->reg + PEHR_MISC_278);
+ writel(SEL_INTERNAL_RESET, pcie_phy->reg + PEHR_MISC_280);
+ writel(POSTED_DATA_CREDITS(0xc0) | POSTED_HEADER_CREDITS(0xa),
+ pcie_phy->reg + PEHR_MISC_70);
+ writel(COMPLETION_DATA_CREDITS(0x30) | COMPLETION_HEADER_CREDITS(0x8),
+ pcie_phy->reg + PEHR_MISC_78);
+ writel(LOCAL_SCALE_SUP, pcie_phy->reg + PEHR_MISC_58);
+ writel(CONFIG_RC_DEVICE, pcie_phy->reg + PEHR_MISC_5C);
+ cfg_val = readl(pcie_phy->reg + PEHR_MISC_60);
+ FIELD_MODIFY(AST2700_PORT_TYPE_MASK, &cfg_val,
+ PORT_TYPE_ROOT);
+ writel(cfg_val, pcie_phy->reg + PEHR_MISC_60);
+ writel(ASSERT_INTERNAL_RESET | SET_TO_DOWNSTREAM,
+ pcie_phy->reg + PEHR_MISC_278);
+ break;
+ default:
+ dev_err(&phy->dev, "Unsupported submode %d\n", submode);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct phy_ops ast2700_phy_ops = {
+ .init = ast2700_phy_init,
+ .exit = aspeed_pcie_phy_exit,
+ .set_mode = ast2700_phy_set_mode,
+ .owner = THIS_MODULE,
+};
+
+static const struct aspeed_pcie_phy_platform pcie_phy_ast2600 = {
+ .phy_ops = &ast2600_phy_ops,
+};
+
+static const struct aspeed_pcie_phy_platform pcie_phy_ast2700 = {
+ .phy_ops = &ast2700_phy_ops,
+};
+
+static int aspeed_pcie_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct phy_provider *phy_provider;
+ struct aspeed_pcie_phy *pcie_phy;
+ const struct aspeed_pcie_phy_platform *md;
+
+ md = of_device_get_match_data(dev);
+ if (!md)
+ return -ENODEV;
+
+ pcie_phy = devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL);
+ if (!pcie_phy)
+ return -ENOMEM;
+
+ pcie_phy->reg = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(pcie_phy->reg))
+ return PTR_ERR(pcie_phy->reg);
+
+ pcie_phy->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(pcie_phy->clk))
+ return dev_err_probe(dev, PTR_ERR(pcie_phy->clk),
+ "failed to get clock\n");
+
+ pcie_phy->platform = md;
+
+ pcie_phy->phy = devm_phy_create(dev, dev->of_node,
+ pcie_phy->platform->phy_ops);
+ if (IS_ERR(pcie_phy->phy))
+ return dev_err_probe(dev, PTR_ERR(pcie_phy->phy),
+ "failed to create PHY\n");
+
+ phy_set_drvdata(pcie_phy->phy, pcie_phy);
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id aspeed_pcie_phy_of_match_table[] = {
+ {
+ .compatible = "aspeed,ast2600-pcie-phy",
+ .data = &pcie_phy_ast2600,
+ },
+ {
+ .compatible = "aspeed,ast2700-pcie-phy",
+ .data = &pcie_phy_ast2700,
+ },
+ { },
+};
+MODULE_DEVICE_TABLE(of, aspeed_pcie_phy_of_match_table);
+
+static struct platform_driver aspeed_pcie_driver = {
+ .probe = aspeed_pcie_phy_probe,
+ .driver = {
+ .name = "aspeed-pcie-phy",
+ .of_match_table = aspeed_pcie_phy_of_match_table,
+ },
+};
+
+module_platform_driver(aspeed_pcie_driver);
+
+MODULE_AUTHOR("Jacky Chou <jacky_chou@aspeedtech.com>");
+MODULE_DESCRIPTION("ASPEED PCIe PHY");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v10 3/3] MAINTAINERS: Add ASPEED PCIe PHY driver
2026-10-20 11:59 [PATCH v10 0/3] Add ASPEED PCIe PHY support Jacky Chou
2026-10-20 11:59 ` [PATCH v10 1/3] dt-bindings: phy: aspeed: Add ASPEED PCIe PHY Jacky Chou
2026-10-20 11:59 ` [PATCH v10 2/3] phy: aspeed: Add ASPEED PCIe PHY driver Jacky Chou
@ 2026-10-20 11:59 ` Jacky Chou
2 siblings, 0 replies; 5+ messages in thread
From: Jacky Chou @ 2026-10-20 11:59 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery,
Ryan Chen, Billy Tsai
Cc: linux-aspeed, linux-phy, devicetree, linux-arm-kernel,
linux-kernel, Jacky Chou
Add maintainer entry for ASPEED PCIe PHY driver.
Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
---
MAINTAINERS | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0570815ee980..33a0336110a7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4044,6 +4044,14 @@ S: Maintained
F: Documentation/devicetree/bindings/crypto/aspeed,*
F: drivers/crypto/aspeed/
+ASPEED PCIE PHY DRIVER
+M: Jacky Chou <jacky_chou@aspeedtech.com>
+L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
+L: linux-phy@lists.infradead.org
+S: Maintained
+F: Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml
+F: drivers/phy/aspeed/phy-aspeed-pcie.c
+
ASPEED PECI CONTROLLER
M: Iwona Winiarska <iwona.winiarska@intel.com>
L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread