[PATCH v4 2/3] firmware: xilinx: Add XilSEM firmware interface

[Rama devi Veggalam <rama.devi.veggalam@amd.com>]

Add the firmware EEMI interface used by the Versal XilSEM (Xilinx
Soft Error Mitigation) EDAC driver. XilSEM runs as part of the
Platform Loader and Manager (PLM) on the PMC and performs CRAM/NPI
scan and error-injection operations on request from Linux.

Add drivers/firmware/xilinx/zynqmp-sem.c with the
zynqmp_pm_xilsem_*() wrapper functions (scan control, error
injection, ECC read, config read, SSIT status read, CRC read, total
SSIT frame count).

Add XilSEM error event node ID and error masks, used to register for
event notification.

Update xlnx_event_manager.c to recognize the new SW_ERR node ID as a
valid error event for both the Versal and Versal NET family codes.

Signed-off-by: Rama devi Veggalam <rama.devi.veggalam@amd.com>
---
Changes in v4:
- Added XilSEM error-event node ID and error masks to the existing
  include/linux/firmware/xlnx-zynqmp.h, used to register for error
  event notification.
- Updated xlnx_event_manager.c to recognize the new SW_ERR node ID as
  a valid error event for both Versal and Versal NET.
- Added full SSIT (multi-die) support.
- Changed all firmware responses to use typed struct xsem_*_response *
  output parameters (7 response structs) instead of raw buffers.
- Added xsem_narrow_dma_addr() to validate and narrow coherent DMA
  addresses for the two calls that take a DMA buffer.
- Added NPI error injection as its own scan-control operation, CRAM
  error injection has its own dedicated call and is not reachable
  through the generic control-ops entry point.

Changes in v3:
- created separate file for Xilsem ATF EEMI calls.

Changes in v2:
- Patch created on top of dependent patch series
"enhance zynqmp_pm_get_family_info()"
- Removed non-relevant SOB names in error event header files
- Updated copyright information
- Merged Versal and Versal NET error event definitions to firmware patch

---
 drivers/firmware/xilinx/Makefile         |   2 +-
 drivers/firmware/xilinx/zynqmp-sem.c     | 229 +++++++++++++++++++++++++++++++
 drivers/soc/xilinx/xlnx_event_manager.c  |  16 ++-
 include/linux/firmware/xlnx-zynqmp-sem.h | 196 ++++++++++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h     |  50 +++++++
 5 files changed, 490 insertions(+), 3 deletions(-)
 create mode 100644 drivers/firmware/xilinx/zynqmp-sem.c
 create mode 100644 include/linux/firmware/xlnx-zynqmp-sem.h

diff --git a/drivers/firmware/xilinx/Makefile b/drivers/firmware/xilinx/Makefile
index 8db0e66..a71919a 100644
--- a/drivers/firmware/xilinx/Makefile
+++ b/drivers/firmware/xilinx/Makefile
@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
 # Makefile for Xilinx firmwares
 
-obj-$(CONFIG_ZYNQMP_FIRMWARE) += zynqmp.o zynqmp-ufs.o zynqmp-crypto.o
+obj-$(CONFIG_ZYNQMP_FIRMWARE) += zynqmp.o zynqmp-ufs.o zynqmp-crypto.o zynqmp-sem.o
 obj-$(CONFIG_ZYNQMP_FIRMWARE_DEBUG) += zynqmp-debug.o
diff --git a/drivers/firmware/xilinx/zynqmp-sem.c b/drivers/firmware/xilinx/zynqmp-sem.c
new file mode 100644
index 0000000..599033f
--- /dev/null
+++ b/drivers/firmware/xilinx/zynqmp-sem.c
@@ -0,0 +1,229 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Firmware layer for XilSEM APIs.
+ *
+ * Copyright (C), 2026 Advanced Micro Devices, Inc.
+ */
+
+#include <linux/export.h>
+#include <linux/firmware/xlnx-zynqmp.h>
+#include <linux/firmware/xlnx-zynqmp-sem.h>
+#include <linux/string.h>
+#include <linux/wordpart.h>
+
+/**
+ * xsem_narrow_dma_addr - Validate and narrow a coherent DMA address for the
+ *			  XilSEM SMC calling convention
+ * @bufaddr:	Coherent DMA buffer address. Must be representable in 32 bits
+ *		(e.g. obtained under dma_set_mask_and_coherent(..,
+ *		DMA_BIT_MASK(32))) - the XilSEM SMC calls cross the calling
+ *		convention as a single u32, so any upper bits are rejected
+ *		rather than silently dropped.
+ * @out:	Output: the lower 32 bits of bufaddr. Valid only if this
+ *		function returns 0.
+ *
+ * Return: 0 on success, -EINVAL if bufaddr is not representable in 32 bits.
+ */
+static int xsem_narrow_dma_addr(dma_addr_t bufaddr, u32 *out)
+{
+	if (upper_32_bits(bufaddr))
+		return -EINVAL;
+
+	*out = lower_32_bits(bufaddr);
+
+	return 0;
+}
+
+/**
+ * zynqmp_pm_xilsem_cntrl_ops - PM call to perform XilSEM operations
+ * @cmd:	Command for XilSEM scan control operations
+ * @slrid:	SLR (Super Logic Region, i.e. die) id on which scan operation to be done
+ * @response:	Output response
+ *
+ * Return: Returns 0 on success or error value on failure.
+ */
+int zynqmp_pm_xilsem_cntrl_ops(u32 cmd, u32 slrid, struct xsem_cntrl_ops_response *response)
+{
+	u32 ret_buf[PAYLOAD_ARG_CNT];
+	int ret;
+
+	switch (cmd) {
+	case PM_XSEM_CRAM_INIT_SCAN:
+	case PM_XSEM_CRAM_START_SCAN:
+	case PM_XSEM_CRAM_STOP_SCAN:
+	case PM_XSEM_NPI_START_SCAN:
+	case PM_XSEM_NPI_STOP_SCAN:
+	case PM_XSEM_NPI_ERR_INJECT:
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	ret = zynqmp_pm_invoke_fn(PM_XSEM_HEADER | cmd, ret_buf, 1, slrid);
+	if (ret)
+		return ret;
+
+	memcpy(response, &ret_buf[1], sizeof(*response));
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_xilsem_cntrl_ops);
+
+/**
+ * zynqmp_pm_xilsem_cram_err_inj - PM call to perform CRAM error injection
+ * @slrid:	SLR id to inject error in CRAM
+ * @frame:	Frame number to be used for error injection
+ * @qword:	Word number to be used for error injection
+ * @bit:	Bit location to be used for error injection
+ * @row:	CFRAME row number to be used for error injection
+ * @response:	Output response
+ *
+ * Return: Returns 0 on success or error value on failure.
+ */
+int zynqmp_pm_xilsem_cram_err_inj(u32 slrid, u32 frame, u32 qword, u32 bit, u32 row,
+				  struct xsem_cram_errinj_response *response)
+{
+	u32 ret_buf[PAYLOAD_ARG_CNT];
+	int ret;
+
+	ret = zynqmp_pm_invoke_fn(PM_XSEM_CRAM_ERRINJ, ret_buf, 5, slrid, frame, qword, bit, row);
+	if (ret)
+		return ret;
+
+	memcpy(response, &ret_buf[1], sizeof(*response));
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_xilsem_cram_err_inj);
+
+/**
+ * zynqmp_pm_xilsem_cram_read_ecc - PM call to perform CFRAME ECC read
+ * @slrid:	SLR id on which Frame ECC read to be done
+ * @frame:	Frame number to be used for reading ECC
+ * @row:	CFRAME row number to be used for reading ECC
+ * @response:	Output response
+ *
+ * Return: Returns 0 on success or error value on failure.
+ */
+int zynqmp_pm_xilsem_cram_read_ecc(u32 slrid, u32 frame, u32 row,
+				   struct xsem_cram_readecc_response *response)
+{
+	u32 ret_buf[PAYLOAD_ARG_CNT];
+	int ret;
+
+	ret = zynqmp_pm_invoke_fn(PM_XSEM_CRAM_RD_ECC, ret_buf, 3, slrid, frame, row);
+	if (ret)
+		return ret;
+
+	memcpy(response, &ret_buf[1], sizeof(*response));
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_xilsem_cram_read_ecc);
+
+/**
+ * zynqmp_pm_xilsem_read_cfg - PM call to perform Xilsem configuration read
+ * @slrid:	SLR id for which configuration to be read
+ * @response:	Output response
+ *
+ * Return: Returns 0 on success or error value on failure.
+ */
+int zynqmp_pm_xilsem_read_cfg(u32 slrid, struct xsem_read_cfg_response *response)
+{
+	u32 ret_buf[PAYLOAD_ARG_CNT];
+	int ret;
+
+	ret = zynqmp_pm_invoke_fn(PM_XSEM_RD_CONFIG, ret_buf, 1, slrid);
+	if (ret)
+		return ret;
+
+	memcpy(response, &ret_buf[1], sizeof(*response));
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_xilsem_read_cfg);
+
+/**
+ * zynqmp_pm_xilsem_read_ssit_status - PM call to perform Xilsem SSIT status
+ * @slrid:	SLR id for which ECC read to be done
+ * @bufaddr:	Coherent DMA buffer address to get the status information.
+ *		See xsem_narrow_dma_addr().
+ * @response:	Output response
+ *
+ * Return: Returns 0 on success or error value on failure.
+ */
+int zynqmp_pm_xilsem_read_ssit_status(u32 slrid, dma_addr_t bufaddr,
+				      struct xsem_read_ssit_status_response *response)
+{
+	u32 ret_buf[PAYLOAD_ARG_CNT];
+	u32 addr;
+	int ret;
+
+	ret = xsem_narrow_dma_addr(bufaddr, &addr);
+	if (ret)
+		return ret;
+
+	ret = zynqmp_pm_invoke_fn(PM_XSEM_SSIT_RD_STS, ret_buf, 2, slrid, addr);
+	if (ret)
+		return ret;
+
+	memcpy(response, &ret_buf[1], sizeof(*response));
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_xilsem_read_ssit_status);
+
+/**
+ * zynqmp_pm_xilsem_cram_get_crc - PM call to perform CRAM Row CRC read
+ * @slrid:	SLR id for which CRC read to be done
+ * @rowindex:	CFRAME row number to be used for reading CRC
+ * @response:	Output response
+ *
+ * Return: Returns 0 on success or error value on failure.
+ */
+int zynqmp_pm_xilsem_cram_get_crc(u32 slrid, u32 rowindex,
+				  struct xsem_cram_getcrc_response *response)
+{
+	u32 ret_buf[PAYLOAD_ARG_CNT];
+	int ret;
+
+	ret = zynqmp_pm_invoke_fn(PM_XSEM_SSIT_GET_CRC, ret_buf, 2, slrid, rowindex);
+	if (ret)
+		return ret;
+
+	memcpy(response, &ret_buf[1], sizeof(*response));
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_xilsem_cram_get_crc);
+
+/**
+ * zynqmp_pm_xilsem_cram_ssit_tot_frames - PM call to perform total frames read
+ * @slrid:	SLR id for which total frames read to be done
+ * @row:	CFRAME row number to be used for reading ECC
+ * @bufaddr:	Coherent DMA buffer address to get total frames data.
+ *		See xsem_narrow_dma_addr().
+ * @response:	Output response
+ *
+ * Return: Returns 0 on success or error value on failure.
+ */
+int zynqmp_pm_xilsem_cram_ssit_tot_frames(u32 slrid, u32 row, dma_addr_t bufaddr,
+					  struct xsem_cram_ssit_totframes_response *response)
+{
+	u32 ret_buf[PAYLOAD_ARG_CNT];
+	u32 addr;
+	int ret;
+
+	ret = xsem_narrow_dma_addr(bufaddr, &addr);
+	if (ret)
+		return ret;
+
+	ret = zynqmp_pm_invoke_fn(PM_XSEM_SSIT_GET_FRAMES, ret_buf, 3, slrid, row, addr);
+	if (ret)
+		return ret;
+
+	memcpy(response, &ret_buf[1], sizeof(*response));
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_xilsem_cram_ssit_tot_frames);
diff --git a/drivers/soc/xilinx/xlnx_event_manager.c b/drivers/soc/xilinx/xlnx_event_manager.c
index f733dc4..d832ee6 100644
--- a/drivers/soc/xilinx/xlnx_event_manager.c
+++ b/drivers/soc/xilinx/xlnx_event_manager.c
@@ -75,6 +75,16 @@ struct registered_event_data {
 	struct hlist_node hentry;
 };
 
+/*
+ * Error-event node ids are per-family firmware IDs, packed at
+ * 0x28100000 + n * 0x4000. The same value names different nodes on
+ * different families: 0x28110000 is VERSAL_EVENT_ERROR_SW_ERR and
+ * VERSAL_NET_EVENT_ERROR_PSM_ERR2. Compare a node_id only inside the
+ * arm for the family that owns it. For this predicate the overlap does
+ * not change the result, because 0x28110000 is an error-event node on
+ * every family that defines it. The family split is required for ids
+ * that exist in only one table.
+ */
 static bool xlnx_is_error_event(const u32 node_id)
 {
 	u32 pm_family_code;
@@ -85,7 +95,8 @@ static bool xlnx_is_error_event(const u32 node_id)
 		if (node_id == VERSAL_EVENT_ERROR_PMC_ERR1 ||
 		    node_id == VERSAL_EVENT_ERROR_PMC_ERR2 ||
 		    node_id == VERSAL_EVENT_ERROR_PSM_ERR1 ||
-		    node_id == VERSAL_EVENT_ERROR_PSM_ERR2)
+		    node_id == VERSAL_EVENT_ERROR_PSM_ERR2 ||
+		    node_id == VERSAL_EVENT_ERROR_SW_ERR)
 			return true;
 	} else if (pm_family_code == PM_VERSAL_NET_FAMILY_CODE) {
 		if (node_id == VERSAL_NET_EVENT_ERROR_PMC_ERR1 ||
@@ -94,7 +105,8 @@ static bool xlnx_is_error_event(const u32 node_id)
 		    node_id == VERSAL_NET_EVENT_ERROR_PSM_ERR1 ||
 		    node_id == VERSAL_NET_EVENT_ERROR_PSM_ERR2 ||
 		    node_id == VERSAL_NET_EVENT_ERROR_PSM_ERR3 ||
-		    node_id == VERSAL_NET_EVENT_ERROR_PSM_ERR4)
+		    node_id == VERSAL_NET_EVENT_ERROR_PSM_ERR4 ||
+		    node_id == VERSAL_NET_EVENT_ERROR_SW_ERR)
 			return true;
 	}
 
diff --git a/include/linux/firmware/xlnx-zynqmp-sem.h b/include/linux/firmware/xlnx-zynqmp-sem.h
new file mode 100644
index 0000000..f2b66cd
--- /dev/null
+++ b/include/linux/firmware/xlnx-zynqmp-sem.h
@@ -0,0 +1,196 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Firmware layer for XilSEM APIs.
+ *
+ * Copyright (C), 2026 Advanced Micro Devices, Inc.
+ */
+
+#ifndef __FIRMWARE_ZYNQMP_SEM_H__
+#define __FIRMWARE_ZYNQMP_SEM_H__
+
+#include <linux/types.h>
+
+/* XilSEM commands */
+#define PM_XSEM_HEADER			0x300
+#define PM_XSEM_CRAM_ERRINJ		0x304
+#define PM_XSEM_RD_CONFIG		0x309
+#define PM_XSEM_CRAM_RD_ECC		0x30B
+#define PM_XSEM_SSIT_GET_CRC		0x30C
+#define PM_XSEM_SSIT_RD_STS		0x30D
+#define PM_XSEM_SSIT_GET_FRAMES		0x30E
+
+/*
+ * Valid cmd values for zynqmp_pm_xilsem_cntrl_ops(). CRAM error injection
+ * has its own dedicated firmware call (zynqmp_pm_xilsem_cram_err_inj()) and
+ * must not be reachable through this generic entry point, so it is
+ * deliberately not a member of this enum.
+ */
+enum pm_xsem_cntrl_op {
+	PM_XSEM_CRAM_INIT_SCAN = 1,
+	PM_XSEM_CRAM_START_SCAN = 2,
+	PM_XSEM_CRAM_STOP_SCAN = 3,
+	PM_XSEM_NPI_START_SCAN = 5,
+	PM_XSEM_NPI_STOP_SCAN = 6,
+	PM_XSEM_NPI_ERR_INJECT = 7,
+};
+
+/**
+ * struct xsem_cntrl_ops_response - Response to zynqmp_pm_xilsem_cntrl_ops()
+ * @hdr:	Command header
+ * @status:	Error code or status
+ * @slrid:	SLR id
+ * @status1:	Reserved for future use
+ * @status2:	Reserved for future use
+ * @status3:	Reserved for future use
+ */
+struct xsem_cntrl_ops_response {
+	u32 hdr;
+	u32 status;
+	u32 slrid;
+	u32 status1;
+	u32 status2;
+	u32 status3;
+};
+
+/**
+ * struct xsem_cram_errinj_response - Response to zynqmp_pm_xilsem_cram_err_inj()
+ * @hdr:	Command header
+ * @status:	Error code or status
+ * @slrid:	SLR id
+ */
+struct xsem_cram_errinj_response {
+	u32 hdr;
+	u32 status;
+	u32 slrid;
+};
+
+/**
+ * struct xsem_cram_readecc_response - Response to zynqmp_pm_xilsem_cram_read_ecc()
+ * @hdr:	Frame ECC read command header
+ * @ecc0:	First ECC word
+ * @ecc1:	Second ECC word
+ * @status:	Status
+ */
+struct xsem_cram_readecc_response {
+	u32 hdr;
+	u32 ecc0;
+	u32 ecc1;
+	u32 status;
+};
+
+/**
+ * struct xsem_read_cfg_response - Response to zynqmp_pm_xilsem_read_cfg()
+ * @hdr:	Config read command header
+ * @cram_cfg:	CRAM scan configuration
+ * @npi_cfg:	NPI scan configuration
+ * @status:	Status
+ */
+struct xsem_read_cfg_response {
+	u32 hdr;
+	u32 cram_cfg;
+	u32 npi_cfg;
+	u32 status;
+};
+
+/**
+ * struct xsem_read_ssit_status_response - Response to
+ *					    zynqmp_pm_xilsem_read_ssit_status()
+ * @hdr:	Status read command header
+ * @slrid:	SLR id
+ */
+struct xsem_read_ssit_status_response {
+	u32 hdr;
+	u32 slrid;
+};
+
+/**
+ * struct xsem_cram_getcrc_response - Response to zynqmp_pm_xilsem_cram_get_crc()
+ * @hdr:	Get CRC command header
+ * @crc0:	First CRC word
+ * @crc1:	Second CRC word
+ * @crc2:	Third CRC word
+ * @crc3:	Fourth CRC word
+ * @status:	Status
+ */
+struct xsem_cram_getcrc_response {
+	u32 hdr;
+	u32 crc0;
+	u32 crc1;
+	u32 crc2;
+	u32 crc3;
+	u32 status;
+};
+
+/**
+ * struct xsem_cram_ssit_totframes_response - Response to
+ *					       zynqmp_pm_xilsem_cram_ssit_tot_frames()
+ * @hdr:	Total frames command header
+ * @slrid:	SLR id
+ * @row:	CFRAME row number
+ * @status:	Status
+ */
+struct xsem_cram_ssit_totframes_response {
+	u32 hdr;
+	u32 slrid;
+	u32 row;
+	u32 status;
+};
+
+#if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
+int zynqmp_pm_xilsem_cntrl_ops(u32 cmd, u32 slrid, struct xsem_cntrl_ops_response *response);
+int zynqmp_pm_xilsem_cram_err_inj(u32 slrid, u32 frame, u32 qword, u32 bit, u32 row,
+				  struct xsem_cram_errinj_response *response);
+int zynqmp_pm_xilsem_cram_read_ecc(u32 slrid, u32 frame, u32 row,
+				   struct xsem_cram_readecc_response *response);
+int zynqmp_pm_xilsem_read_cfg(u32 slrid, struct xsem_read_cfg_response *response);
+int zynqmp_pm_xilsem_read_ssit_status(u32 slrid, dma_addr_t bufaddr,
+				      struct xsem_read_ssit_status_response *response);
+int zynqmp_pm_xilsem_cram_get_crc(u32 slrid, u32 rowindex,
+				  struct xsem_cram_getcrc_response *response);
+int zynqmp_pm_xilsem_cram_ssit_tot_frames(u32 slrid, u32 row, dma_addr_t bufaddr,
+					  struct xsem_cram_ssit_totframes_response *response);
+#else
+static inline int zynqmp_pm_xilsem_cntrl_ops(u32 cmd, u32 slrid,
+					     struct xsem_cntrl_ops_response *response)
+{
+	return -ENODEV;
+}
+
+static inline int zynqmp_pm_xilsem_cram_err_inj(u32 slrid, u32 frame, u32 qword, u32 bit, u32 row,
+						struct xsem_cram_errinj_response *response)
+{
+	return -ENODEV;
+}
+
+static inline int zynqmp_pm_xilsem_cram_read_ecc(u32 slrid, u32 frame, u32 row,
+						 struct xsem_cram_readecc_response *response)
+{
+	return -ENODEV;
+}
+
+static inline int zynqmp_pm_xilsem_read_cfg(u32 slrid, struct xsem_read_cfg_response *response)
+{
+	return -ENODEV;
+}
+
+static inline int zynqmp_pm_xilsem_read_ssit_status(u32 slrid, dma_addr_t bufaddr,
+						    struct xsem_read_ssit_status_response *response)
+{
+	return -ENODEV;
+}
+
+static inline int zynqmp_pm_xilsem_cram_get_crc(u32 slrid, u32 rowindex,
+						struct xsem_cram_getcrc_response *response)
+{
+	return -ENODEV;
+}
+
+static inline int
+zynqmp_pm_xilsem_cram_ssit_tot_frames(u32 slrid, u32 row, dma_addr_t bufaddr,
+				      struct xsem_cram_ssit_totframes_response *response)
+{
+	return -ENODEV;
+}
+#endif
+
+#endif /* __FIRMWARE_ZYNQMP_SEM_H__ */
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index f4b3df6..80ca1dc 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -121,6 +121,12 @@
 #define VERSAL_EVENT_ERROR_PMC_ERR2	(0x28104000U)
 #define VERSAL_EVENT_ERROR_PSM_ERR1	(0x28108000U)
 #define VERSAL_EVENT_ERROR_PSM_ERR2	(0x2810C000U)
+/*
+ * SW Error Event Node Id (0x4000 stride from PSM_ERR2 above). This
+ * value coincidentally equals VERSAL_NET_EVENT_ERROR_PSM_ERR2 below -
+ * harmless, since each family's node IDs are an independent sequence.
+ */
+#define VERSAL_EVENT_ERROR_SW_ERR	(0x28110000U)
 
 #define VERSAL_NET_EVENT_ERROR_PMC_ERR1	(0x28100000U)
 #define VERSAL_NET_EVENT_ERROR_PMC_ERR2	(0x28104000U)
@@ -129,6 +135,8 @@
 #define VERSAL_NET_EVENT_ERROR_PSM_ERR2	(0x28110000U)
 #define VERSAL_NET_EVENT_ERROR_PSM_ERR3	(0x28114000U)
 #define VERSAL_NET_EVENT_ERROR_PSM_ERR4	(0x28118000U)
+/* SW Error Event Node Id */
+#define VERSAL_NET_EVENT_ERROR_SW_ERR	(0x2811C000U)
 
 /* ZynqMP SD tap delay tuning */
 #define SD_ITAPDLY	0xFF180314
@@ -146,6 +154,48 @@
 #define XPM_EVENT_ERROR_MASK_NOC_NCR		BIT(13)
 #define XPM_EVENT_ERROR_MASK_NOC_CR		BIT(12)
 
+/*
+ * XPM_VERSAL_EVENT_ERROR_MASK_XSEM_CRAM_CE_5: Error event mask for handling
+ * correctable error in Versal Configuration RAM which is reported by
+ * Soft Error Mitigation (XilSEM).
+ */
+#define XPM_VERSAL_EVENT_ERROR_MASK_XSEM_CRAM_CE_5		BIT(5)
+
+/*
+ * XPM_VERSAL_EVENT_ERROR_MASK_XSEM_CRAM_UE_6: Error event mask for handling
+ * uncorrectable error in Versal Configuration RAM which is reported by
+ * Soft Error Mitigation (XilSEM).
+ */
+#define XPM_VERSAL_EVENT_ERROR_MASK_XSEM_CRAM_UE_6		BIT(6)
+
+/*
+ * XPM_VERSAL_EVENT_ERROR_MASK_XSEM_NPI_UE_7: Error event mask for handling
+ * uncorrectable error in Versal NoC programming interface (NPI)
+ * register which is reported by Soft Error Mitigation (XilSEM).
+ */
+#define XPM_VERSAL_EVENT_ERROR_MASK_XSEM_NPI_UE_7		BIT(7)
+
+/*
+ * XPM_VERSAL_NET_EVENT_ERROR_MASK_XSEM_CRAM_CE: Error event mask for handling
+ * correctable error in Versal Configuration RAM which is reported by
+ * Soft Error Mitigation (XilSEM).
+ */
+#define XPM_VERSAL_NET_EVENT_ERROR_MASK_XSEM_CRAM_CE		BIT(7)
+
+/*
+ * XPM_VERSAL_NET_EVENT_ERROR_MASK_XSEM_CRAM_UE: Error event mask for handling
+ * uncorrectable error in Versal Configuration RAM which is reported by
+ * Soft Error Mitigation (XilSEM).
+ */
+#define XPM_VERSAL_NET_EVENT_ERROR_MASK_XSEM_CRAM_UE		BIT(8)
+
+/*
+ * XPM_VERSAL_NET_EVENT_ERROR_MASK_XSEM_NPI_UE: Error event mask for handling
+ * uncorrectable error in Versal NoC programming interface (NPI)
+ * register which is reported by Soft Error Mitigation (XilSEM).
+ */
+#define XPM_VERSAL_NET_EVENT_ERROR_MASK_XSEM_NPI_UE		BIT(9)
+
 /* Node ID for all peripheral devices */
 #define PM_DEV_ALL_PERIPH	0x18224FFFU
 
-- 
1.9.5