[PATCH 0/5] spi: tegra114: chip-select fixes and PIO-only probe

[Vishwaroop A <va@nvidia.com>]

Tegra114 SPI sends each transfer as its own packet, and hardware CS
follows that packet. The driver implements transfer_one_message(), so
it has to do the per-transfer delay and cs_change itself. It gets
both wrong.

The delay runs after CS is dropped. A mid-message cs_change drops CS
and never drives it active again. When the last transfer holds CS,
the next message can turn hardware CS back on and drop the line.
TIS-SPI under spi_bus_lock() needs CS held across those messages.
Multi-transfer messages already use software CS; patch 4 only moves
that choice so patch 5 can keep it.

Patch 1 is separate. A missing "dmas" property fails probe even
though PIO works, so fall back to PIO.

Krishna Yarlagadda (1):
  spi: tegra114: Allow PIO fallback when DMA is unavailable

Vishwaroop A (4):
  spi: tegra114: Run per-transfer delay before ending the transfer
  spi: tegra114: Assert CS between transfers when cs_change is set
  spi: tegra114: Decide the chip-select mode once per message
  spi: tegra114: Keep software CS across bus-locked messages

 drivers/spi/spi-tegra114.c | 126 ++++++++++++++++++++++++++-----------
 1 file changed, 89 insertions(+), 37 deletions(-)


base-commit: b810335a0699d1810683796b0e3ffe8827ddfe6c
-- 
2.17.1