From: Christian Cortner <ccortner@gmail.com>
To: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>,
Vinod Koul <vkoul@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>
Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] phy: qcom: edp: update v8 power-on programming sequence
Date: Sat, 31 Oct 2026 11:24:31 -0500 [thread overview]
Message-ID: <179346367993.44447.8683103034067826560.x2e-share-edp@gmail.com> (raw)
In-Reply-To: <fc3d0dfc-20cb-4289-a0dd-67ace50d42d8@oss.qualcomm.com>
Hi Konrad, Bjorn,
On the Asus Zenbook A16 (glymur, eDP at 5.4 Gbps), this series with
Konrad's TXn_LDO_CONFIG value (0x91) fell back to 2 lanes on 14 of
120 link enables, with bit errors on lanes 1 and 3.
The firmware ends power-on with five registers set differently:
DP_PHY_CFG_1 0x2f -> 0x0f (the bit 5 Konrad flagged)
DP_PHY_TX2_TX3_LANE_CTL 0x05 -> 0x00
TXn_RESET_TSYNC_EN 0x0a -> 0x03
DP_PHY_TSYNC_OVRD 0x3e -> 0x10
DP_PHY_CFG after DCC 0x09 -> 0x19
Writing the firmware values at the end of power-on, all 120 enables
over two boots trained 4 lanes cleanly, and 10 of 10 resumes. Which
register matters is not known. Happy to test a revision.
Christian
next prev parent reply other threads:[~2026-10-31 16:24 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-22 23:29 [PATCH 0/2] phy: qcom: edp: Update v8 " Bjorn Andersson
2026-06-22 23:29 ` [PATCH 1/2] phy: qcom: edp: split power-on sequencing by PHY version Bjorn Andersson
2026-06-23 7:37 ` Konrad Dybcio
2026-06-22 23:29 ` [PATCH 2/2] phy: qcom: edp: update v8 power-on programming sequence Bjorn Andersson
2026-06-23 9:10 ` Konrad Dybcio
2026-10-31 16:24 ` Christian Cortner [this message]
2026-11-04 7:27 ` Burke Cates
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