From: patchwork-bot+linux-riscv@kernel.org
To: Pengpeng Hou <hppiscas@163.com>
Cc: linux-riscv@lists.infradead.org, radu@rendec.net,
tglx@kernel.org, cmirabil@redhat.com,
linux-kernel@vger.kernel.org, lzampier@redhat.com,
pjw@kernel.org, samuel.holland@sifive.com
Subject: Re: [PATCH v2] irqchip/sifive-plic: Avoid signed shift in interrupt enable mask
Date: Sun, 01 Nov 2026 22:16:05 +0000 [thread overview]
Message-ID: <179357136504.2624073.16513286116615894552.git-patchwork-notify@kernel.org> (raw)
In-Reply-To: <caplitmus-rv.v2.plic.87a8fc444de44e109889ba28703c76f3@163.com>
Hello:
This patch was applied to riscv/linux.git (fixes)
by Thomas Gleixner <tglx@kernel.org>:
On Sun, 20 Sep 2026 21:06:53 +0800 you wrote:
> __plic_toggle() builds a 32-bit interrupt enable mask using a signed
> integer literal. A valid interrupt selecting bit 31 evaluates 1 << 31,
> which shifts a signed int into its sign bit.
>
> Use BIT(), matching the equivalent mask construction in plic_irq_eoi().
> The resulting mask remains representable in u32 on both RV32 and RV64.
>
> [...]
Here is the summary with links:
- [v2] irqchip/sifive-plic: Avoid signed shift in interrupt enable mask
https://git.kernel.org/riscv/c/0f214e5bbee5
You are awesome, thank you!
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prev parent reply other threads:[~2026-11-01 22:16 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-20 13:06 Pengpeng Hou
2026-10-14 8:58 ` Pengpeng Hou
2026-10-15 9:54 ` [tip: irq/drivers] " tip-bot2 for Pengpeng Hou
2026-11-01 22:16 ` patchwork-bot+linux-riscv [this message]
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