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* [PATCH v5] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema
@ 2026-11-07 13:49 Dileep Kumar Nagavarapu
  2026-11-07 19:26 ` Jonathan Cameron
  2026-11-10 18:40 ` Rob Herring (Arm)
  0 siblings, 2 replies; 3+ messages in thread
From: Dileep Kumar Nagavarapu @ 2026-11-07 13:49 UTC (permalink / raw)
  To: lars, sai.krishna.potthuri, dileepkumar.nagavarapu, jic23,
	dlechner, nuno.sa, andy, robh, krzk+dt, conor+dt, michal.simek,
	pramod.nexgen
  Cc: linux-iio, devicetree, linux-kernel, git

From: Pramod Maurya <pramod.nexgen@gmail.com>

Convert the Xilinx XADC and UltraScale System Monitor device tree binding
from the legacy plain-text format to a YAML.

The new binding covers the same hardware and compatible strings:
  - xlnx,zynq-xadc-1.00.a (ZYNQ hardblock)
  - xlnx,axi-xadc-1.00.a  (AXI softblock)
  - xlnx,system-management-wiz-1.3 (UltraScale System Management Wizard)

The xlnx,channels subnode retains its legacy name (including the comma)
for backwards compatibility with existing device trees.

Move xlnx,channels under properties, as dt-schema now allows node names
containing a comma for long-established bindings.Constrain the reg
property of the channel subnodes to the valid channel range of 0 to
16 with minimum and maximum.

Drop the redundant "type: boolean" from xlnx,bipolar, since its $ref to
the flag type already implies it.

Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
Co-developed-by: Dileep Kumar Nagavarapu <dileepkumar.nagavarapu@amd.com>
Signed-off-by: Dileep Kumar Nagavarapu <dileepkumar.nagavarapu@amd.com>
---
This patch was originally posted by Pramod Maurya.

Link:https://lore.kernel.org/all/20260515075736.172172-2-pramod.nexgen@gmail.com/

I will be maintaining the patch going forward and posting updated
revisions.

Changes in v5:
- Simplify the commit message: drop the mention of automated validation
  and remove the dt-schema PR reference
- Use "hardblock" and "softblock" instead of "hardmacro" and "softmacro"
  for the Zynq and AXI XADC variants
- Drop the clock description
(Comments from Jonathan Cameron)
- Drop the "|" literal block indicator from the clocks and
  xlnx,external-mux descriptions, as the formatting does not need to be
  preserved
- Add "default: none" for xlnx,external-mux and remove the sentence about
  the behavior when it is omitted
- Reduce the examples to a single one. Remove the ZYNQ/AXI/UltraScale
  origin comments and the two redundant examples. Add xlnx,bipolar to
  a channel in the remaining example
- Add Sai Krishna Potthuri and Dileep Kumar Nagavarapu as additional
  maintainers in the binding and the MAINTAINERS entry, alongside
  Lars-Peter Clausen
(Comments from Sashiko AI review)
- Constrain reg in the channel subnodes to the valid range 0-16 with
  minimum/maximum
- Reword the commit message to describe the valid range constraint
  (minimum and maximum)

Changes in v4:
- Move xlnx,channels from patternProperties: to properties: per Rob
  Herring's guidance (keywords.yaml: "Fixed strings belong in properties")
  This requires a companion dt-schema update to add xlnx,channels as an
  object-type exception in vendor-props.yaml (like adi,channels).
- Fix reg constraints inside channel subnodes: remove items block with
  minimum/maximum which is invalid for cell arrays per cell.yaml; the
  valid channel range (0-16) is documented in the description instead.
- Remove redundant type: boolean from xlnx,bipolar; the $ref to
  /schemas/types.yaml#/definitions/flag already implies boolean type.
- Fix patternProperties regex for channel subnodes to "^channel@([0-9a-f]|10)$"
  covering all valid hex unit addresses for channels 0-16.

Changes in v3:
- Move xlnx,channels from properties: to patternProperties: to satisfy
  vendor-props.yaml meta-schema (reversed in v4, see above)

Changes in v2:
- Fix patternProperties regex to use lowercase hex unit addresses
- Add allOf/if/then conditional requiring xlnx,external-mux-channel
  when xlnx,external-mux is "single" or "dual"
---
 .../bindings/iio/adc/xilinx-xadc.txt          | 141 ---------------
 .../bindings/iio/adc/xlnx,xadc.yaml           | 165 ++++++++++++++++++
 MAINTAINERS                                   |   9 +
 3 files changed, 174 insertions(+), 141 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
 create mode 100644 Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml

diff --git a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt b/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
deleted file mode 100644
index f42e18078376..000000000000
--- a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
+++ /dev/null
@@ -1,141 +0,0 @@
-Xilinx XADC device driver
-
-This binding document describes the bindings for the Xilinx 7 Series XADC as well
-as the UltraScale/UltraScale+ System Monitor.
-
-The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
-The XADC has a DRP interface for communication. Currently two different
-frontends for the DRP interface exist. One that is only available on the ZYNQ
-family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
-on all series 7 platforms and is a softmacro with a AXI interface. This binding
-document describes the bindings for both of them since the bindings are very
-similar.
-
-The Xilinx System Monitor is an ADC that is found in the UltraScale and
-UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for
-communication. Xilinx provides a standard IP core that can be used to access the
-System Monitor through an AXI interface in the FPGA fabric. This IP core is
-called the Xilinx System Management Wizard. This document describes the bindings
-for this IP.
-
-Required properties:
-	- compatible: Should be one of
-		* "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
-		  configuration interface to interface to the XADC hardmacro.
-		* "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
-		  interface to the XADC hardmacro.
-		* "xlnx,system-management-wiz-1.3": When using the
-		  Xilinx System Management Wizard fabric IP core to access the
-		  UltraScale and UltraScale+ System Monitor.
-	- reg: Address and length of the register set for the device
-	- interrupts: Interrupt for the XADC control interface.
-	- clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
-	  when using the axi-xadc or the axi-system-management-wizard this must be
-	  the clock that provides the clock to the AXI bus interface of the core.
-
-Optional properties:
-	- xlnx,external-mux:
-		* "none": No external multiplexer is used, this is the default
-		  if the property is omitted.
-		* "single": External multiplexer mode is used with one
-		   multiplexer.
-		* "dual": External multiplexer mode is used with two
-		  multiplexers for simultaneous sampling.
-	- xlnx,external-mux-channel: Configures which pair of pins is used to
-	  sample data in external mux mode.
-	  Valid values for single external multiplexer mode are:
-		0: VP/VN
-		1: VAUXP[0]/VAUXN[0]
-		2: VAUXP[1]/VAUXN[1]
-		...
-		16: VAUXP[15]/VAUXN[15]
-	  Valid values for dual external multiplexer mode are:
-		1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]
-		2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]
-		...
-		8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]
-
-	  This property needs to be present if the device is configured for
-	  external multiplexer mode (either single or dual). If the device is
-	  not using external multiplexer mode the property is ignored.
-	- xnlx,channels: List of external channels that are connected to the ADC
-	  Required properties:
-		* #address-cells: Should be 1.
-		* #size-cells: Should be 0.
-
-	  The child nodes of this node represent the external channels which are
-	  connected to the ADC. If the property is no present no external
-	  channels will be assumed to be connected.
-
-	  Each child node represents one channel and has the following
-	  properties:
-		Required properties:
-			* reg: Pair of pins the channel is connected to.
-				0: VP/VN
-				1: VAUXP[0]/VAUXN[0]
-				2: VAUXP[1]/VAUXN[1]
-				...
-				16: VAUXP[15]/VAUXN[15]
-			  Note each channel number should only be used at most
-			  once.
-		Optional properties:
-			* xlnx,bipolar: If set the channel is used in bipolar
-			  mode.
-
-
-Examples:
-	xadc@f8007100 {
-		compatible = "xlnx,zynq-xadc-1.00.a";
-		reg = <0xf8007100 0x20>;
-		interrupts = <0 7 4>;
-		interrupt-parent = <&gic>;
-		clocks = <&pcap_clk>;
-
-		xlnx,channels {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			channel@0 {
-				reg = <0>;
-			};
-			channel@1 {
-				reg = <1>;
-			};
-			channel@8 {
-				reg = <8>;
-			};
-		};
-	};
-
-	xadc@43200000 {
-		compatible = "xlnx,axi-xadc-1.00.a";
-		reg = <0x43200000 0x1000>;
-		interrupts = <0 53 4>;
-		interrupt-parent = <&gic>;
-		clocks = <&fpga1_clk>;
-
-		xlnx,channels {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			channel@0 {
-				reg = <0>;
-				xlnx,bipolar;
-			};
-		};
-	};
-
-	adc@80000000 {
-		compatible = "xlnx,system-management-wiz-1.3";
-		reg = <0x80000000 0x1000>;
-		interrupts = <0 81 4>;
-		interrupt-parent = <&gic>;
-		clocks = <&fpga1_clk>;
-
-		xlnx,channels {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			channel@0 {
-				reg = <0>;
-				xlnx,bipolar;
-			};
-		};
-	};
diff --git a/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml b/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
new file mode 100644
index 000000000000..2cbc3b82a26f
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
@@ -0,0 +1,165 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/xlnx,xadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx XADC and UltraScale System Monitor
+
+maintainers:
+  - Lars-Peter Clausen <lars@metafoo.de>
+  - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
+  - Dileep Kumar Nagavarapu <dileepkumar.nagavarapu@amd.com>
+
+description: |
+  The Xilinx XADC is an ADC found in the Series 7 FPGAs. It has a DRP
+  (Dynamic Reconfiguration Port) interface for communication. Two different
+  frontends for the DRP interface are supported:
+
+    - ZYNQ hardblock: available only on the ZYNQ family as a hardblock in
+      the SoC portion of the ZYNQ device.
+    - AXI softblock: available on all Series 7 platforms as a softblock
+      with an AXI interface (PG019).
+
+  The Xilinx System Monitor is an ADC found in UltraScale and UltraScale+
+  FPGAs. It is accessed through the Xilinx System Management Wizard IP core
+  via an AXI interface in the FPGA fabric.
+
+  The xlnx,channels subnode name contains a comma as part of the legacy
+  device tree binding that has been in use for over a decade. This name is
+  retained for backwards compatibility with existing device trees.
+
+properties:
+  compatible:
+    enum:
+      - xlnx,zynq-xadc-1.00.a
+      - xlnx,axi-xadc-1.00.a
+      - xlnx,system-management-wiz-1.3
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  xlnx,external-mux:
+    $ref: /schemas/types.yaml#/definitions/string
+    description:
+      Selects the external multiplexer mode.
+    enum:
+      - none
+      - single
+      - dual
+    default: none
+
+  xlnx,external-mux-channel:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      Configures which pair of pins is used to sample data in external
+      multiplexer mode. Required when xlnx,external-mux is "single" or
+      "dual".
+
+      Valid values for single external multiplexer mode:
+        0: VP/VN
+        1: VAUXP[0]/VAUXN[0]
+        2: VAUXP[1]/VAUXN[1]
+        ...
+        16: VAUXP[15]/VAUXN[15]
+
+      Valid values for dual external multiplexer mode:
+        1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]
+        2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]
+        ...
+        8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]
+    minimum: 0
+    maximum: 16
+
+  xlnx,channels:
+    type: object
+    description:
+      List of external channels connected to the ADC. If this node is
+      absent, no external channels are assumed to be connected.
+
+    properties:
+      '#address-cells':
+        const: 1
+
+      '#size-cells':
+        const: 0
+
+    patternProperties:
+      "^channel@([0-9a-f]|10)$":
+        type: object
+        description:
+          Represents an external channel connected to the ADC.
+
+        properties:
+          reg:
+            description: |
+              Pair of pins the channel is connected to.
+                0: VP/VN
+                1: VAUXP[0]/VAUXN[0]
+                2: VAUXP[1]/VAUXN[1]
+                ...
+                16: VAUXP[15]/VAUXN[15]
+            minimum: 0
+            maximum: 16
+
+          xlnx,bipolar:
+            $ref: /schemas/types.yaml#/definitions/flag
+            description:
+              If set, the channel is used in bipolar mode.
+
+        required:
+          - reg
+
+        additionalProperties: false
+
+    required:
+      - '#address-cells'
+      - '#size-cells'
+
+    additionalProperties: false
+
+allOf:
+  - if:
+      properties:
+        xlnx,external-mux:
+          enum:
+            - single
+            - dual
+      required:
+        - xlnx,external-mux
+    then:
+      required:
+        - xlnx,external-mux-channel
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    xadc@43200000 {
+        compatible = "xlnx,axi-xadc-1.00.a";
+        reg = <0x43200000 0x1000>;
+        interrupts = <0 53 4>;
+        interrupt-parent = <&gic>;
+        clocks = <&fpga1_clk>;
+
+        xlnx,channels {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            channel@0 {
+                reg = <0>;
+                xlnx,bipolar;
+            };
+        };
+    };
diff --git a/MAINTAINERS b/MAINTAINERS
index 745d8d0169b2..2d7e9c9ca659 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -29996,6 +29996,15 @@ F:	Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml
 F:	drivers/watchdog/of_xilinx_wdt.c
 F:	drivers/watchdog/xilinx_wwdt.c
 
+XILINX XADC DRIVER
+M:	Lars-Peter Clausen <lars@metafoo.de>
+M:	Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
+M:	Dileep Kumar Nagavarapu <dileepkumar.nagavarapu@amd.com>
+L:	linux-iio@vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
+F:	drivers/iio/adc/xilinx-xadc*
+
 XILINX XDMA DRIVER
 M:	Lizhi Hou <lizhi.hou@amd.com>
 M:	Brian Xu <brian.xu@amd.com>

base-commit: 309bd01041636b587bcb424b243640b448bd62f7
-- 
2.34.1


^ permalink raw reply	[flat|nested] 3+ messages in thread
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2026-11-07 13:49 [PATCH v5] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema Dileep Kumar Nagavarapu
2026-11-07 19:26 ` Jonathan Cameron
2026-11-10 18:40 ` Rob Herring (Arm)

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