[PATCH 0/2] dt-bindings: convert the Zynq-7000 SLCR child bindings to yaml

[PATCH 0/2] dt-bindings: convert the Zynq-7000 SLCR child bindings to yaml

[Radhey Shyam Pandey]

Convert the two remaining free-form bindings for children of the Zynq-7000
SLCR syscon, the reset controller and the PS clock controller, to schema.
Both keep reg as an offset into the parent SLCR, which is what the drivers
expect. ps-clk-frequency becomes optional with its 33 MHz default, and the
missing trace_emio_clk input is added. 

Radhey Shyam Pandey (2):
  dt-bindings: reset: convert zynq-reset.txt to yaml
  dt-bindings: clock: convert zynq-7000.txt to yaml

 .../bindings/clock/xlnx,ps7-clkc.yaml         | 145 ++++++++++++++++++
 .../devicetree/bindings/clock/zynq-7000.txt   | 110 -------------
 .../bindings/reset/xlnx,zynq-reset.yaml       |  99 ++++++++++++
 .../devicetree/bindings/reset/zynq-reset.txt  |  68 --------
 4 files changed, 244 insertions(+), 178 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/xlnx,ps7-clkc.yaml
 delete mode 100644 Documentation/devicetree/bindings/clock/zynq-7000.txt
 create mode 100644 Documentation/devicetree/bindings/reset/xlnx,zynq-reset.yaml
 delete mode 100644 Documentation/devicetree/bindings/reset/zynq-reset.txt


base-commit: 067c5c24cef23d913b67eaaf71ae67e7169a6620
-- 
2.44.4

[PATCH 1/2] dt-bindings: reset: convert zynq-reset.txt to yaml

[Radhey Shyam Pandey]

Convert the Xilinx Zynq reset manager binding to DT schema format.

The reset output list is kept, hung off #reset-cells since that is what
the numbers describe. It is preceded by the encoding the text version
left implicit: the cell is the register's position in the block times 32
plus the bit number within that register. This also explains the gaps in
the list, which are reserved bits and, in the case of 0x23c, a reserved
register.

No dt-bindings header is added. Unlike the firmware-defined IDs in
xlnx,zynqmp-reset, these indices are derived from the SLCR register map
in UG585, and no in-tree device tree references them.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
---
 .../bindings/reset/xlnx,zynq-reset.yaml       | 99 +++++++++++++++++++
 .../devicetree/bindings/reset/zynq-reset.txt  | 68 -------------
 2 files changed, 99 insertions(+), 68 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/reset/xlnx,zynq-reset.yaml
 delete mode 100644 Documentation/devicetree/bindings/reset/zynq-reset.txt

diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynq-reset.yaml b/Documentation/devicetree/bindings/reset/xlnx,zynq-reset.yaml
new file mode 100644
index 000000000000..a91c999f6243
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/xlnx,zynq-reset.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/xlnx,zynq-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Zynq Reset Manager
+
+maintainers:
+  - Michal Simek <michal.simek@amd.com>
+
+description:
+  The Zynq AP-SoC has several different resets, driven from registers in the
+  System Level Control Registers (SLCR). The reset manager is a child node of
+  the SLCR. See Chapter 26 of the Zynq TRM (UG585) for more information about
+  Zynq resets.
+
+properties:
+  compatible:
+    const: xlnx,zynq-reset
+
+  reg:
+    maxItems: 1
+    description:
+      Offset and length of the reset registers within the SLCR.
+
+  syscon:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: phandle to the SLCR registers
+
+  "#reset-cells":
+    const: 1
+    description: |
+      The single cell indexes the reset within the register block at 32
+      resets per register, so it is the register's position in the block
+      times 32 plus the bit number within that register:
+
+        0   soft
+        32  ddr
+        64  topsw
+        96  dmac
+        128 usb0
+        129 usb1
+        160 gem0
+        161 gem1
+        164 gem0 rx
+        165 gem1 rx
+        166 gem0 ref
+        167 gem1 ref
+        192 sdio0
+        193 sdio1
+        196 sdio0 ref
+        197 sdio1 ref
+        224 spi0
+        225 spi1
+        226 spi0 ref
+        227 spi1 ref
+        256 can0
+        257 can1
+        258 can0 ref
+        259 can1 ref
+        288 i2c0
+        289 i2c1
+        320 uart0
+        321 uart1
+        322 uart0 ref
+        323 uart1 ref
+        352 gpio
+        384 lqspi
+        385 qspi ref
+        416 smc
+        417 smc ref
+        448 ocm
+        512 fpga0 out
+        513 fpga1 out
+        514 fpga2 out
+        515 fpga3 out
+        544 a9 reset 0
+        545 a9 reset 1
+        552 peri
+
+required:
+  - compatible
+  - reg
+  - syscon
+  - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    reset-controller@200 {
+        compatible = "xlnx,zynq-reset";
+        reg = <0x200 0x48>;
+        #reset-cells = <1>;
+        syscon = <&slcr>;
+    };
+
+...
diff --git a/Documentation/devicetree/bindings/reset/zynq-reset.txt b/Documentation/devicetree/bindings/reset/zynq-reset.txt
deleted file mode 100644
index 5860120e3064..000000000000
--- a/Documentation/devicetree/bindings/reset/zynq-reset.txt
+++ /dev/null
@@ -1,68 +0,0 @@
-Xilinx Zynq Reset Manager
-
-The Zynq AP-SoC has several different resets.
-
-See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
-
-Required properties:
-- compatible: "xlnx,zynq-reset"
-- reg: SLCR offset and size taken via syscon <0x200 0x48>
-- syscon: <&slcr>
-  This should be a phandle to the Zynq's SLCR registers.
-- #reset-cells: Must be 1
-
-The Zynq Reset Manager needs to be a childnode of the SLCR.
-
-Example:
-	rstc: rstc@200 {
-		compatible = "xlnx,zynq-reset";
-		reg = <0x200 0x48>;
-		#reset-cells = <1>;
-		syscon = <&slcr>;
-	};
-
-Reset outputs:
- 0  : soft reset
- 32 : ddr reset
- 64 : topsw reset
- 96 : dmac reset
- 128: usb0 reset
- 129: usb1 reset
- 160: gem0 reset
- 161: gem1 reset
- 164: gem0 rx reset
- 165: gem1 rx reset
- 166: gem0 ref reset
- 167: gem1 ref reset
- 192: sdio0 reset
- 193: sdio1 reset
- 196: sdio0 ref reset
- 197: sdio1 ref reset
- 224: spi0 reset
- 225: spi1 reset
- 226: spi0 ref reset
- 227: spi1 ref reset
- 256: can0 reset
- 257: can1 reset
- 258: can0 ref reset
- 259: can1 ref reset
- 288: i2c0 reset
- 289: i2c1 reset
- 320: uart0 reset
- 321: uart1 reset
- 322: uart0 ref reset
- 323: uart1 ref reset
- 352: gpio reset
- 384: lqspi reset
- 385: qspi ref reset
- 416: smc reset
- 417: smc ref reset
- 448: ocm reset
- 512: fpga0 out reset
- 513: fpga1 out reset
- 514: fpga2 out reset
- 515: fpga3 out reset
- 544: a9 reset 0
- 545: a9 reset 1
- 552: peri reset
-
-- 
2.44.4

[PATCH 2/2] dt-bindings: clock: convert zynq-7000.txt to yaml

[Radhey Shyam Pandey]

Convert the Zynq 7000 clock controller binding to DT schema format.

ps-clk-frequency becomes optional with a documented 33 MHz default. The
text version listed it as required, but zynq-7000.dtsi does not set it
and five in-tree boards (zynq-cc108 and zynq-zc770-xm010 through xm013)
never override it, so requiring it would reject device trees that are
already in use.

trace_emio_clk is added to the clock inputs. It is the external trace
clock feeding the debug trace mux, which the text version never listed.
The example is corrected the same way: it used can_mio_clk_23, which
does not match the mio_clk_XX form this binding defines for an EMIO
clock on a MIO pin.

clock-output-names is enumerated as 48 const entries instead of the
prose "shall be a list of the outputs below", so the names and their
order are now checked. The clock cell is an index into that list.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
---
 .../bindings/clock/xlnx,ps7-clkc.yaml         | 145 ++++++++++++++++++
 .../devicetree/bindings/clock/zynq-7000.txt   | 110 -------------
 2 files changed, 145 insertions(+), 110 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/xlnx,ps7-clkc.yaml
 delete mode 100644 Documentation/devicetree/bindings/clock/zynq-7000.txt

diff --git a/Documentation/devicetree/bindings/clock/xlnx,ps7-clkc.yaml b/Documentation/devicetree/bindings/clock/xlnx,ps7-clkc.yaml
new file mode 100644
index 000000000000..2d6ce2ba5d87
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/xlnx,ps7-clkc.yaml
@@ -0,0 +1,145 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/xlnx,ps7-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Zynq 7000 clock controller
+
+maintainers:
+  - Michal Simek <michal.simek@amd.com>
+
+description:
+  The clock controller generates the PS clocks from the three PLLs and the
+  clock generators in the System Level Control Registers (SLCR). It is a
+  child node of the SLCR. See Chapter 25 of the Zynq TRM (UG585) for more
+  information about Zynq clocks.
+
+properties:
+  compatible:
+    const: xlnx,ps7-clkc
+
+  reg:
+    maxItems: 1
+
+  "#clock-cells":
+    const: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 58
+
+  clock-names:
+    minItems: 1
+    maxItems: 58
+    description:
+      Optional (E)MIO clock sources. mio_clk_XX names the EMIO clock on MIO
+      pin XX and may be given for pins 00 to 53.
+    items:
+      oneOf:
+        - enum: [ gem0_emio_clk, gem1_emio_clk, swdt_ext_clk, trace_emio_clk ]
+        - pattern: '^mio_clk_([0-4][0-9]|5[0-3])$'
+
+  clock-output-names:
+    description:
+      Names for the 48 clock outputs, in the order the single clock cell
+      indexes them.
+    items:
+      - const: armpll
+      - const: ddrpll
+      - const: iopll
+      - const: cpu_6or4x
+      - const: cpu_3or2x
+      - const: cpu_2x
+      - const: cpu_1x
+      - const: ddr2x
+      - const: ddr3x
+      - const: dci
+      - const: lqspi
+      - const: smc
+      - const: pcap
+      - const: gem0
+      - const: gem1
+      - const: fclk0
+      - const: fclk1
+      - const: fclk2
+      - const: fclk3
+      - const: can0
+      - const: can1
+      - const: sdio0
+      - const: sdio1
+      - const: uart0
+      - const: uart1
+      - const: spi0
+      - const: spi1
+      - const: dma
+      - const: usb0_aper
+      - const: usb1_aper
+      - const: gem0_aper
+      - const: gem1_aper
+      - const: sdio0_aper
+      - const: sdio1_aper
+      - const: spi0_aper
+      - const: spi1_aper
+      - const: can0_aper
+      - const: can1_aper
+      - const: i2c0_aper
+      - const: i2c1_aper
+      - const: uart0_aper
+      - const: uart1_aper
+      - const: gpio_aper
+      - const: lqspi_aper
+      - const: smc_aper
+      - const: swdt
+      - const: dbg_trc
+      - const: dbg_apb
+
+  ps-clk-frequency:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 33333333
+    description:
+      Frequency of the oscillator providing ps_clk, in Hz. Zynq platforms
+      usually fit a 33 MHz oscillator.
+
+  fclk-enable:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0
+    maximum: 0xf
+    description:
+      Bit mask of FCLKs to enable at boot time. Bits 0 to 3 correspond to
+      FCLK0 to FCLK3.
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"
+  - clock-output-names
+
+additionalProperties: false
+
+examples:
+  - |
+    clkc: clock-controller@100 {
+        compatible = "xlnx,ps7-clkc";
+        reg = <0x100 0x100>;
+        #clock-cells = <1>;
+        ps-clk-frequency = <33333333>;
+        fclk-enable = <0>;
+        clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
+                             "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x",
+                             "ddr3x", "dci", "lqspi", "smc", "pcap",
+                             "gem0", "gem1", "fclk0", "fclk1", "fclk2",
+                             "fclk3", "can0", "can1", "sdio0", "sdio1",
+                             "uart0", "uart1", "spi0", "spi1", "dma",
+                             "usb0_aper", "usb1_aper", "gem0_aper",
+                             "gem1_aper", "sdio0_aper", "sdio1_aper",
+                             "spi0_aper", "spi1_aper", "can0_aper",
+                             "can1_aper", "i2c0_aper", "i2c1_aper",
+                             "uart0_aper", "uart1_aper", "gpio_aper",
+                             "lqspi_aper", "smc_aper", "swdt", "dbg_trc",
+                             "dbg_apb";
+        clocks = <&clkc 16>, <&clk_foo>;
+        clock-names = "gem1_emio_clk", "mio_clk_23";
+    };
+
+...
diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt
deleted file mode 100644
index d93746cf2975..000000000000
--- a/Documentation/devicetree/bindings/clock/zynq-7000.txt
+++ /dev/null
@@ -1,110 +0,0 @@
-Device Tree Clock bindings for the Zynq 7000 EPP
-
-The Zynq EPP has several different clk providers, each with there own bindings.
-The purpose of this document is to document their usage.
-
-See clock_bindings.txt for more information on the generic clock bindings.
-See Chapter 25 of Zynq TRM for more information about Zynq clocks.
-
-== Clock Controller ==
-The clock controller is a logical abstraction of Zynq's clock tree. It reads
-required input clock frequencies from the devicetree and acts as clock provider
-for all clock consumers of PS clocks.
-
-Required properties:
- - #clock-cells : Must be 1
- - compatible : "xlnx,ps7-clkc"
- - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
- - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
-		      (usually 33 MHz oscillators are used for Zynq platforms)
- - clock-output-names : List of strings used to name the clock outputs. Shall be
-			a list of the outputs given below.
-
-Optional properties:
- - clocks : as described in the clock bindings
- - clock-names : as described in the clock bindings
- - fclk-enable : Bit mask to enable FCLKs statically at boot time.
-		 Bit [0..3] correspond to FCLK0..FCLK3. The corresponding
-		 FCLK will only be enabled if it is actually running at
-		 boot time.
-
-Clock inputs:
-The following strings are optional parameters to the 'clock-names' property in
-order to provide an optional (E)MIO clock source.
- - swdt_ext_clk
- - gem0_emio_clk
- - gem1_emio_clk
- - mio_clk_XX		# with XX = 00..53
-...
-
-Clock outputs:
- 0:  armpll
- 1:  ddrpll
- 2:  iopll
- 3:  cpu_6or4x
- 4:  cpu_3or2x
- 5:  cpu_2x
- 6:  cpu_1x
- 7:  ddr2x
- 8:  ddr3x
- 9:  dci
- 10: lqspi
- 11: smc
- 12: pcap
- 13: gem0
- 14: gem1
- 15: fclk0
- 16: fclk1
- 17: fclk2
- 18: fclk3
- 19: can0
- 20: can1
- 21: sdio0
- 22: sdio1
- 23: uart0
- 24: uart1
- 25: spi0
- 26: spi1
- 27: dma
- 28: usb0_aper
- 29: usb1_aper
- 30: gem0_aper
- 31: gem1_aper
- 32: sdio0_aper
- 33: sdio1_aper
- 34: spi0_aper
- 35: spi1_aper
- 36: can0_aper
- 37: can1_aper
- 38: i2c0_aper
- 39: i2c1_aper
- 40: uart0_aper
- 41: uart1_aper
- 42: gpio_aper
- 43: lqspi_aper
- 44: smc_aper
- 45: swdt
- 46: dbg_trc
- 47: dbg_apb
-
-Example:
-	clkc: clkc@100 {
-		#clock-cells = <1>;
-		compatible = "xlnx,ps7-clkc";
-		ps-clk-frequency = <33333333>;
-		reg = <0x100 0x100>;
-		clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
-				"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
-				"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
-				"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
-				"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
-				"dma", "usb0_aper", "usb1_aper", "gem0_aper",
-				"gem1_aper", "sdio0_aper", "sdio1_aper",
-				"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
-				"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
-				"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
-				"dbg_trc", "dbg_apb";
-		# optional props
-		clocks = <&clkc 16>, <&clk_foo>;
-		clock-names = "gem1_emio_clk", "can_mio_clk_23";
-	};
-- 
2.44.4

Re: [PATCH 2/2] dt-bindings: clock: convert zynq-7000.txt to yaml

[Rob Herring (Arm)]

On Wed, 11 Nov 2026 20:38:12 +0530, Radhey Shyam Pandey wrote:
> Convert the Zynq 7000 clock controller binding to DT schema format.
> 
> ps-clk-frequency becomes optional with a documented 33 MHz default. The
> text version listed it as required, but zynq-7000.dtsi does not set it
> and five in-tree boards (zynq-cc108 and zynq-zc770-xm010 through xm013)
> never override it, so requiring it would reject device trees that are
> already in use.
> 
> trace_emio_clk is added to the clock inputs. It is the external trace
> clock feeding the debug trace mux, which the text version never listed.
> The example is corrected the same way: it used can_mio_clk_23, which
> does not match the mio_clk_XX form this binding defines for an EMIO
> clock on a MIO pin.
> 
> clock-output-names is enumerated as 48 const entries instead of the
> prose "shall be a list of the outputs below", so the names and their
> order are now checked. The clock cell is an index into that list.
> 
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
> ---
>  .../bindings/clock/xlnx,ps7-clkc.yaml         | 145 ++++++++++++++++++
>  .../devicetree/bindings/clock/zynq-7000.txt   | 110 -------------
>  2 files changed, 145 insertions(+), 110 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/xlnx,ps7-clkc.yaml
>  delete mode 100644 Documentation/devicetree/bindings/clock/zynq-7000.txt
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 1/2] dt-bindings: reset: convert zynq-reset.txt to yaml

[Rob Herring (Arm)]

On Wed, 11 Nov 2026 20:38:11 +0530, Radhey Shyam Pandey wrote:
> Convert the Xilinx Zynq reset manager binding to DT schema format.
> 
> The reset output list is kept, hung off #reset-cells since that is what
> the numbers describe. It is preceded by the encoding the text version
> left implicit: the cell is the register's position in the block times 32
> plus the bit number within that register. This also explains the gaps in
> the list, which are reserved bits and, in the case of 0x23c, a reserved
> register.
> 
> No dt-bindings header is added. Unlike the firmware-defined IDs in
> xlnx,zynqmp-reset, these indices are derived from the SLCR register map
> in UG585, and no in-tree device tree references them.
> 
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
> ---
>  .../bindings/reset/xlnx,zynq-reset.yaml       | 99 +++++++++++++++++++
>  .../devicetree/bindings/reset/zynq-reset.txt  | 68 -------------
>  2 files changed, 99 insertions(+), 68 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/reset/xlnx,zynq-reset.yaml
>  delete mode 100644 Documentation/devicetree/bindings/reset/zynq-reset.txt
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>