From: Chen-Yu Tsai <wens@kernel.org>
To: Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Maxime Ripard <mripard@kernel.org>,
Andre Przywara <andre.przywara@arm.com>,
Arun Iyengar <aiyengar1990@gmail.com>
Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
stable@vger.kernel.org
Subject: Re: [PATCH 0/2] clk: sunxi-ng: h616: Fix the EMAC 25 MHz and S/PDIF clocks
Date: Sun, 15 Nov 2026 17:41:30 +0800 [thread overview]
Message-ID: <179473569042.3056166.1982990416520172498.b4-ty@kernel.org> (raw)
In-Reply-To: <20261110-h616-clk-emac-spdif-v1-0-e5e36e8963e4@gmail.com>
On Tue, 10 Nov 2026 06:02:59 +0000, Arun Iyengar wrote:
> Two small fixes for the H616 CCU, found while checking the clock tree of
> an Orange Pi Zero2 against the H616 user manual.
>
> Patch 1 models the EPHY 25 MHz clock as PLL_PERI0 / 24, as the manual
> describes it. Only the parent and the reported rate change; the register
> writes are the same.
>
> [...]
Applied to sunxi/clk-for-7.5 in sunxi, thanks!
[1/2] clk: sunxi-ng: h616: Fix the EMAC 25 MHz clock parent and divider
https://git.kernel.org/sunxi/linux/c/93797c1f8455
[2/2] clk: sunxi-ng: h616: Let the S/PDIF clock set the audio PLL rate
https://git.kernel.org/sunxi/linux/c/d0cd486a2b64
Best regards,
--
Chen-Yu Tsai <wens@kernel.org>
prev parent reply other threads:[~2026-11-15 9:41 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-10 6:02 Arun Iyengar via B4 Relay
2026-11-10 6:03 ` [PATCH 1/2] clk: sunxi-ng: h616: Fix the EMAC 25 MHz clock parent and divider Arun Iyengar via B4 Relay
2026-11-10 15:57 ` Jernej Škrabec
2026-11-10 6:03 ` [PATCH 2/2] clk: sunxi-ng: h616: Let the S/PDIF clock set the audio PLL rate Arun Iyengar via B4 Relay
2026-11-10 15:55 ` Jernej Škrabec
2026-11-15 9:41 ` Chen-Yu Tsai [this message]
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