From: David Laight <David.Laight@ACULAB.COM>
To: 'Charlie Jenkins' <charlie@rivosinc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Conor Dooley <conor@kernel.org>,
Samuel Holland <samuel.holland@sifive.com>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>
Subject: RE: [PATCH v4 2/5] riscv: Add checksum library
Date: Tue, 12 Sep 2023 08:45:38 +0000 [thread overview]
Message-ID: <1818c4114b0e4144a9df21f235984840@AcuMS.aculab.com> (raw)
In-Reply-To: <20230911-optimize_checksum-v4-2-77cc2ad9e9d7@rivosinc.com>
From: Charlie Jenkins
> Sent: 11 September 2023 23:57
>
> Provide a 32 and 64 bit version of do_csum. When compiled for 32-bit
> will load from the buffer in groups of 32 bits, and when compiled for
> 64-bit will load in groups of 64 bits. Benchmarking by proxy compiling
> csum_ipv6_magic (64-bit version) for an x86 chip as well as running
> the riscv generated code in QEMU, discovered that summing in a
> tree-like structure is about 4% faster than doing 64-bit reads.
>
...
> + sum = saddr->s6_addr32[0];
> + sum += saddr->s6_addr32[1];
> + sum1 = saddr->s6_addr32[2];
> + sum1 += saddr->s6_addr32[3];
> +
> + sum2 = daddr->s6_addr32[0];
> + sum2 += daddr->s6_addr32[1];
> + sum3 = daddr->s6_addr32[2];
> + sum3 += daddr->s6_addr32[3];
> +
> + sum4 = csum;
> + sum4 += ulen;
> + sum4 += uproto;
> +
> + sum += sum1;
> + sum2 += sum3;
> +
> + sum += sum2;
> + sum += sum4;
Have you got gcc to compile that as-is?
Whenever I've tried to get a 'tree add' compiled so that the
early adds can be executed in parallel gcc always pessimises
it to a linear sequence of adds.
But I agree that adding 32bit values to a 64bit register
may be no slower than trying to do an 'add carry' sequence
that is guaranteed to only do one add/clock.
(And on Intel cpu from core-2 until IIRC Haswell adc took 2 clocks!)
IIRC RISCV doesn't have a carry flag, so the adc sequence
is hard - probably takes two extra instructions per value.
Although with parallel execute it may not matter.
Consider:
val = buf[offset];
sum += val;
carry += sum < val;
val = buf[offset1];
sum += val;
...
the compare and 'carry +=' can be executed at the same time
as the following two instructions.
You do then a final sum += carry; sum += sum < carry;
Assuming all instructions are 1 clock and any read delays
get filled with other instructions (by source or hardware
instruction re-ordering) even without parallel execute
that is 4 clocks for 64 bits, which is much the same as the
2 clocks for 32 bits.
Remember that all the 32bit values can summed first as
they won't overflow.
David
-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)
next prev parent reply other threads:[~2023-09-12 8:45 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-11 22:57 [PATCH v4 0/5] riscv: Add fine-tuned checksum functions Charlie Jenkins
2023-09-11 22:57 ` [PATCH v4 1/5] riscv: Checksum header Charlie Jenkins
2023-09-12 10:24 ` Emil Renner Berthing
2023-09-13 2:38 ` Charlie Jenkins
2023-09-13 9:19 ` Emil Renner Berthing
2023-09-11 22:57 ` [PATCH v4 2/5] riscv: Add checksum library Charlie Jenkins
2023-09-12 8:45 ` David Laight [this message]
2023-09-13 3:09 ` Charlie Jenkins
2023-09-13 8:47 ` David Laight
2023-09-13 23:18 ` Charlie Jenkins
2023-09-14 0:41 ` Charlie Jenkins
2023-09-14 12:25 ` Conor Dooley
2023-09-14 17:58 ` Charlie Jenkins
2023-09-14 18:02 ` Conor Dooley
2023-09-14 23:30 ` Charlie Jenkins
2023-09-11 22:57 ` [PATCH v4 3/5] riscv: Vector checksum header Charlie Jenkins
2023-09-11 22:57 ` [PATCH v4 4/5] riscv: Vector checksum library Charlie Jenkins
2023-09-14 12:46 ` Conor Dooley
2023-09-14 16:14 ` Charlie Jenkins
2023-09-14 16:29 ` Conor Dooley
2023-09-14 17:29 ` Charlie Jenkins
2023-09-14 17:36 ` Conor Dooley
2023-09-14 20:59 ` Charlie Jenkins
2023-09-11 22:57 ` [PATCH v4 5/5] riscv: Test checksum functions Charlie Jenkins
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