[PATCH] x86/cpu: Add several Intel server CPU mode numbers

[PATCH] x86/cpu: Add several Intel server CPU mode numbers

[Tony Luck]

These servers are all on the public versions of the roadmap. The model
numbers for Grand Ridge, Granite Rapids, and Sierra Forest were included
in the September 2022 edition of the Instruction Set Extensions document.

Signed-off-by: Tony Luck <tony.luck@intel.com>
---
 arch/x86/include/asm/intel-family.h | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
index 5d75fe229342..347707d459c6 100644
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -107,6 +107,11 @@
 
 #define INTEL_FAM6_SAPPHIRERAPIDS_X	0x8F	/* Golden Cove */
 
+#define INTEL_FAM6_EMERALDRAPIDS_X	0xCF
+
+#define INTEL_FAM6_GRANITERAPIDS_X	0xAD
+#define INTEL_FAM6_GRANITERAPIDS_D	0xAE
+
 #define INTEL_FAM6_ALDERLAKE		0x97	/* Golden Cove / Gracemont */
 #define INTEL_FAM6_ALDERLAKE_L		0x9A	/* Golden Cove / Gracemont */
 #define INTEL_FAM6_ALDERLAKE_N		0xBE
@@ -118,7 +123,7 @@
 #define INTEL_FAM6_METEORLAKE		0xAC
 #define INTEL_FAM6_METEORLAKE_L		0xAA
 
-/* "Small Core" Processors (Atom) */
+/* "Small Core" Processors (Atom/E-Core) */
 
 #define INTEL_FAM6_ATOM_BONNELL		0x1C /* Diamondville, Pineview */
 #define INTEL_FAM6_ATOM_BONNELL_MID	0x26 /* Silverthorne, Lincroft */
@@ -145,6 +150,10 @@
 #define INTEL_FAM6_ATOM_TREMONT		0x96 /* Elkhart Lake */
 #define INTEL_FAM6_ATOM_TREMONT_L	0x9C /* Jasper Lake */
 
+#define INTEL_FAM6_SIERRAFOREST_X	0xAF
+
+#define INTEL_FAM6_GRANDRIDGE		0xB6
+
 /* Xeon Phi */
 
 #define INTEL_FAM6_XEON_PHI_KNL		0x57 /* Knights Landing */
-- 
2.38.1

Re: [PATCH] x86/cpu: Add several Intel server CPU mode numbers

[Dave Hansen]

On 11/3/22 13:33, Tony Luck wrote:
> These servers are all on the public versions of the roadmap. The model
> numbers for Grand Ridge, Granite Rapids, and Sierra Forest were included
> in the September 2022 edition of the Instruction Set Extensions document.
...
>  #define INTEL_FAM6_SAPPHIRERAPIDS_X	0x8F	/* Golden Cove */
>  
> +#define INTEL_FAM6_EMERALDRAPIDS_X	0xCF

Were the core names (like Golden Cove) left out intentionally?  Not a
big deal either way, but it's sometimes nice to see for things like the
hybrid parts what it might be "related" to.

Either way:

Acked-by: Dave Hansen <dave.hansen@linux.intel.com>

RE: [PATCH] x86/cpu: Add several Intel server CPU mode numbers

[Luck, Tony]

>>  #define INTEL_FAM6_SAPPHIRERAPIDS_X	0x8F	/* Golden Cove */
>>  
>> +#define INTEL_FAM6_EMERALDRAPIDS_X	0xCF
>
> Were the core names (like Golden Cove) left out intentionally?  Not a
> big deal either way, but it's sometimes nice to see for things like the
> hybrid parts what it might be "related" to.

Yes. Intentionally left out for now.

I try not to get ahead of what Intel has publicly announced for future
products. So details like that have to wait.

> Either way:
>
> Acked-by: Dave Hansen <dave.hansen@linux.intel.com>

Thanks

-Tony

[tip: x86/urgent] x86/cpu: Add several Intel server CPU model numbers

[tip-bot2 for Tony Luck]

The following commit has been merged into the x86/urgent branch of tip:

Commit-ID:     7beade0dd41d42d797ccb7791b134a77fcebf35b
Gitweb:        https://git.kernel.org/tip/7beade0dd41d42d797ccb7791b134a77fcebf35b
Author:        Tony Luck <tony.luck@intel.com>
AuthorDate:    Thu, 03 Nov 2022 13:33:10 -07:00
Committer:     Borislav Petkov <bp@suse.de>
CommitterDate: Fri, 04 Nov 2022 21:12:22 +01:00

x86/cpu: Add several Intel server CPU model numbers

These servers are all on the public versions of the roadmap. The model
numbers for Grand Ridge, Granite Rapids, and Sierra Forest were included
in the September 2022 edition of the Instruction Set Extensions document.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Dave Hansen <dave.hansen@linux.intel.com>
Link: https://lore.kernel.org/r/20221103203310.5058-1-tony.luck@intel.com
---
 arch/x86/include/asm/intel-family.h | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
index 5d75fe2..347707d 100644
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -107,6 +107,11 @@
 
 #define INTEL_FAM6_SAPPHIRERAPIDS_X	0x8F	/* Golden Cove */
 
+#define INTEL_FAM6_EMERALDRAPIDS_X	0xCF
+
+#define INTEL_FAM6_GRANITERAPIDS_X	0xAD
+#define INTEL_FAM6_GRANITERAPIDS_D	0xAE
+
 #define INTEL_FAM6_ALDERLAKE		0x97	/* Golden Cove / Gracemont */
 #define INTEL_FAM6_ALDERLAKE_L		0x9A	/* Golden Cove / Gracemont */
 #define INTEL_FAM6_ALDERLAKE_N		0xBE
@@ -118,7 +123,7 @@
 #define INTEL_FAM6_METEORLAKE		0xAC
 #define INTEL_FAM6_METEORLAKE_L		0xAA
 
-/* "Small Core" Processors (Atom) */
+/* "Small Core" Processors (Atom/E-Core) */
 
 #define INTEL_FAM6_ATOM_BONNELL		0x1C /* Diamondville, Pineview */
 #define INTEL_FAM6_ATOM_BONNELL_MID	0x26 /* Silverthorne, Lincroft */
@@ -145,6 +150,10 @@
 #define INTEL_FAM6_ATOM_TREMONT		0x96 /* Elkhart Lake */
 #define INTEL_FAM6_ATOM_TREMONT_L	0x9C /* Jasper Lake */
 
+#define INTEL_FAM6_SIERRAFOREST_X	0xAF
+
+#define INTEL_FAM6_GRANDRIDGE		0xB6
+
 /* Xeon Phi */
 
 #define INTEL_FAM6_XEON_PHI_KNL		0x57 /* Knights Landing */