[PATCH v9 0/2] Enable sdhc inline crypto engine for kodiak and monaco

[PATCH v9 0/2] Enable sdhc inline crypto engine for kodiak and monaco

[Kuldeep Singh]

The series is combination of below 2 series sent in past. Since, both
need to be picked together, combine them and send as one series.
- https://lore.kernel.org/lkml/20260608041650.541502-1-neeraj.soni@oss.qualcomm.com/
- https://lore.kernel.org/linux-arm-msm/20260409-ice_emmc_clock_addition-v2-0-90bbcc057361@oss.qualcomm.com/

Document and wire the SDHCI to ICE relationship on Qualcomm platforms
where ICE is modelled as a dedicated DT node.

This series:
- adds the qcom,ice phandle to the SDHCI binding and enforces the
  qcom,ice vs embedded-reg modelling rule,
- enables ICE for kodiak and monaco by wiring SDHC to the dedicated ICE
  node,
- adds interface clock and power-domain requirements for the ICE node in
  affected DTS files.

How this series was tested:
- make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- \
  DT_SCHEMA_FILES=Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml \
  dt_binding_check
- make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- CHECK_DTBS=y \
  qcom/monaco-arduino-monza.dtb qcom/monaco-evk.dtb \
  qcom/qcm6490-fairphone-fp5.dtb qcom/qcm6490-idp.dtb \
  qcom/qcm6490-particle-tachyon.dtb qcom/qcm6490-shift-otter.dtb \
  qcom/qcs6490-radxa-dragon-q6a.dtb qcom/qcs6490-rb3gen2.dtb \
  qcom/qcs6490-thundercomm-minipc-g1iot.dtb \
  qcom/qcs6490-thundercomm-rubikpi3.dtb qcom/qcs8300-ride.dtb \
  qcom/sc7280-crd-r3.dtb qcom/sc7280-herobrine-crd-pro.dtb \
  qcom/sc7280-herobrine-crd.dtb qcom/sc7280-herobrine-evoker-lte.dtb \
  qcom/sc7280-herobrine-evoker.dtb qcom/sc7280-herobrine-herobrine-r1.dtb \
  qcom/sc7280-herobrine-villager-r0.dtb \
  qcom/sc7280-herobrine-villager-r1-lte.dtb \
  qcom/sc7280-herobrine-villager-r1.dtb \
  qcom/sc7280-herobrine-zombie-lte.dtb \
  qcom/sc7280-herobrine-zombie-nvme-lte.dtb \
  qcom/sc7280-herobrine-zombie-nvme.dtb qcom/sc7280-herobrine-zombie.dtb \
  qcom/sc7280-idp.dtb qcom/sc7280-idp2.dtb \
  qcom/sm7325-motorola-dubai.dtb qcom/sm7325-nothing-spacewar.dtb

Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
---
Changes in v9:
- Rebased on linux-next tag next-20260706 (base commit 8e9685d3c41c).
- Drop dt-bindings as already picked in -next by Ulf.
- Enable ice node default for sdhc and ufs and validate DT schema(with
  dt-bindings applied locally).
- Link to v8: https://patch.msgid.link/20260629-ice_emmc_support-v8-0-1a26e1717b85@oss.qualcomm.com

Changes in v8:
- Added iface clock, clock-names, power-domain and disabled status in
  kodiak and monaco ICE nodes.
- Enabled ICE in board DTS files where SDHC is enabled while keeping SoC
  ICE nodes disabled by default.
- Updated trailers to reflect co-development and sender sign-off order.
- Revalidated with dt_binding_check and CHECK_DTBS for all impacted DTS.
- Link to v7: https://lore.kernel.org/all/20260608041650.541502-1-neeraj.soni@oss.qualcomm.com/

Changes in v7:
- Rebased on latest linux-next (sdhci-msm.yaml renamed to qcom,sdhci-msm.yaml).
- Added links for previous versions.
- Link to v6: https://lore.kernel.org/all/20260310113557.348502-1-neeraj.soni@oss.qualcomm.com/

Changes in v6:
- Wrapped commit message for patch (1/3) as per Linux coding guidelines.
- Signed off the patch (3/3).
- Link to v5: https://lore.kernel.org/all/20260306093332.4193993-1-neeraj.soni@oss.qualcomm.com/

Changes in v5:
- Updated the constraint for SDHCI 'v4' vs rest to reflect the 'qcom,ice'
  constraint.
- Link to v4: https://lore.kernel.org/all/20260217052526.2335759-1-neeraj.soni@oss.qualcomm.com/

Changes in v4:
- Added a new patch (3/3) for device tree changes for Monaco SoC.
- Updated commit subject of cover letter to reflect "monaco".
- Removed the text description of constraints from "description:" for "qcom,ice" and
  wrapped the code.
- Corrected the schema code to reflect the constraint of "qcom,ice" usage properly.
- Link to v3: https://lore.kernel.org/all/20260206112053.3287756-1-neeraj.soni@oss.qualcomm.com/

Changes in v3:
- Described the purpose for phandle in "description:" for "qcom,ice".
- Re-added the "if: required:" description for "qcom,ice" with proper
  encoding.
- Corrected the uppercase for base address and reg address space for ICE DT node.
- Link to v2: https://lore.kernel.org/all/20260114094848.3790487-1-neeraj.soni@oss.qualcomm.com/

Changes in v2:
- Removed the "if: required:" description for "qcom,ice" dt-binding
  as the ICE node is optional.
- Corrected the ICE dt node entry according to the dt-binding description.
- Added test details.
- Link to v1: https://lore.kernel.org/all/20251124111914.3187803-1-neeraj.soni@oss.qualcomm.com/

Changes in v1:
- Updated the dt-binding for ICE node.
- Added the dt node for ICE for kodiak.

To: Bjorn Andersson <andersson@kernel.org>
To: Konrad Dybcio <konradybcio@kernel.org>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

---
Neeraj Soni (2):
      arm64: dts: qcom: kodiak: enable inline crypto engine for SDHC
      arm64: dts: qcom: monaco: enable inline crypto engine for SDHC

 arch/arm64/boot/dts/qcom/kodiak.dtsi | 13 +++++++++++++
 arch/arm64/boot/dts/qcom/monaco.dtsi | 13 +++++++++++++
 2 files changed, 26 insertions(+)
---
base-commit: 8e9685d3c41c35dd1b37df70d854137abcb2fbac
change-id: 20260629-ice_emmc_support-b24c84cb5054

Best regards,
--  
Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>

[PATCH v9 1/2] arm64: dts: qcom: kodiak: enable inline crypto engine for SDHC

[Kuldeep Singh]

From: Neeraj Soni <neeraj.soni@oss.qualcomm.com>

Add the dedicated ICE node for kodiak and reference it from the SDHC
controller via qcom,ice.

Also, define power-domains and clocks properties similar to the UFS
node.

Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
Co-developed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/kodiak.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 90e50c245c0c..3692be65cc21 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -1050,6 +1050,8 @@ sdhc_1: mmc@7c4000 {
 			qcom,dll-config = <0x0007642c>;
 			qcom,ddr-config = <0x80040868>;
 
+			qcom,ice = <&sdhc_ice>;
+
 			mmc-ddr-1_8v;
 			mmc-hs200-1_8v;
 			mmc-hs400-1_8v;
@@ -1076,6 +1078,17 @@ opp-384000000 {
 			};
 		};
 
+		sdhc_ice: crypto@7c8000 {
+			compatible = "qcom,sc7280-inline-crypto-engine",
+				     "qcom,inline-crypto-engine";
+			reg = <0x0 0x007c8000 0x0 0x18000>;
+			clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>,
+				 <&gcc GCC_SDCC1_AHB_CLK>;
+			clock-names = "core",
+				      "iface";
+			power-domains = <&rpmhpd SC7280_CX>;
+		};
+
 		gpi_dma0: dma-controller@900000 {
 			#dma-cells = <3>;
 			compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";

-- 
2.34.1

[PATCH v9 2/2] arm64: dts: qcom: monaco: enable inline crypto engine for SDHC

[Kuldeep Singh]

From: Neeraj Soni <neeraj.soni@oss.qualcomm.com>

Add the dedicated ICE node for monaco and reference it from the SDHC
controller via qcom,ice.

Also, define power-domains and clocks properties similar to the UFS
node.

Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
Co-developed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/monaco.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index 400c75437978..ffb13d61ee36 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -4864,6 +4864,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
 			supports-cqe;
 			dma-coherent;
 
+			qcom,ice = <&sdhc_ice>;
+
 			mmc-ddr-1_8v;
 			mmc-hs200-1_8v;
 			mmc-hs400-1_8v;
@@ -4896,6 +4898,17 @@ opp-384000000 {
 			};
 		};
 
+		sdhc_ice: crypto@87c8000 {
+			compatible = "qcom,qcs8300-inline-crypto-engine",
+				     "qcom,inline-crypto-engine";
+			reg = <0x0 0x087c8000 0x0 0x18000>;
+			clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>,
+				 <&gcc GCC_SDCC1_AHB_CLK>;
+			clock-names = "core",
+				      "iface";
+			power-domains = <&rpmhpd RPMHPD_CX>;
+		};
+
 		usb_1_hsphy: phy@8904000 {
 			compatible = "qcom,qcs8300-usb-hs-phy",
 				     "qcom,usb-snps-hs-7nm-phy";

-- 
2.34.1

Re: [PATCH v9 0/2] Enable sdhc inline crypto engine for kodiak and monaco

[Kuldeep Singh]

On 07-07-2026 12:41, Kuldeep Singh wrote:
> The series is combination of below 2 series sent in past. Since, both
> need to be picked together, combine them and send as one series.
> - https://lore.kernel.org/lkml/20260608041650.541502-1-neeraj.soni@oss.qualcomm.com/
> - https://lore.kernel.org/linux-arm-msm/20260409-ice_emmc_clock_addition-v2-0-90bbcc057361@oss.qualcomm.com/
> 
> Document and wire the SDHCI to ICE relationship on Qualcomm platforms
> where ICE is modelled as a dedicated DT node.
> 
> This series:
> - adds the qcom,ice phandle to the SDHCI binding and enforces the
>   qcom,ice vs embedded-reg modelling rule,
> - enables ICE for kodiak and monaco by wiring SDHC to the dedicated ICE
>   node,
> - adds interface clock and power-domain requirements for the ICE node in
>   affected DTS files.

Konrad/Bjorn, could you please review and let me know for any comments.

-- 
Regards
Kuldeep

Re: [PATCH v9 1/2] arm64: dts: qcom: kodiak: enable inline crypto engine for SDHC

[Konrad Dybcio]

On 7/7/26 9:11 AM, Kuldeep Singh wrote:
> From: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
> 
> Add the dedicated ICE node for kodiak and reference it from the SDHC
> controller via qcom,ice.
> 
> Also, define power-domains and clocks properties similar to the UFS
> node.
> 
> Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
> Co-developed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
> Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v9 2/2] arm64: dts: qcom: monaco: enable inline crypto engine for SDHC

[Konrad Dybcio]

On 7/7/26 9:11 AM, Kuldeep Singh wrote:
> From: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
> 
> Add the dedicated ICE node for monaco and reference it from the SDHC
> controller via qcom,ice.
> 
> Also, define power-domains and clocks properties similar to the UFS
> node.
> 
> Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
> Co-developed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
> Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v9 0/2] Enable sdhc inline crypto engine for kodiak and monaco

[Kuldeep Singh]

On 21-07-2026 12:43, Kuldeep Singh wrote:
> On 07-07-2026 12:41, Kuldeep Singh wrote:
>> The series is combination of below 2 series sent in past. Since, both
>> need to be picked together, combine them and send as one series.
>> - https://lore.kernel.org/lkml/20260608041650.541502-1-neeraj.soni@oss.qualcomm.com/
>> - https://lore.kernel.org/linux-arm-msm/20260409-ice_emmc_clock_addition-v2-0-90bbcc057361@oss.qualcomm.com/
>>
>> Document and wire the SDHCI to ICE relationship on Qualcomm platforms
>> where ICE is modelled as a dedicated DT node.
>>
>> This series:
>> - adds the qcom,ice phandle to the SDHCI binding and enforces the
>>   qcom,ice vs embedded-reg modelling rule,
>> - enables ICE for kodiak and monaco by wiring SDHC to the dedicated ICE
>>   node,
>> - adds interface clock and power-domain requirements for the ICE node in
>>   affected DTS files.
> 
> Konrad/Bjorn, could you please review and let me know for any comments.
Thanks Konrad for review.
Bjorn, can you please help in picking patch for v7.3-rc1.

-- 
Regards
Kuldeep

Re: [PATCH v9 0/2] Enable sdhc inline crypto engine for kodiak and monaco

[Konrad Dybcio]

On 8/24/26 10:43 AM, Kuldeep Singh wrote:
> On 21-07-2026 12:43, Kuldeep Singh wrote:
>> On 07-07-2026 12:41, Kuldeep Singh wrote:
>>> The series is combination of below 2 series sent in past. Since, both
>>> need to be picked together, combine them and send as one series.
>>> - https://lore.kernel.org/lkml/20260608041650.541502-1-neeraj.soni@oss.qualcomm.com/
>>> - https://lore.kernel.org/linux-arm-msm/20260409-ice_emmc_clock_addition-v2-0-90bbcc057361@oss.qualcomm.com/
>>>
>>> Document and wire the SDHCI to ICE relationship on Qualcomm platforms
>>> where ICE is modelled as a dedicated DT node.
>>>
>>> This series:
>>> - adds the qcom,ice phandle to the SDHCI binding and enforces the
>>>   qcom,ice vs embedded-reg modelling rule,
>>> - enables ICE for kodiak and monaco by wiring SDHC to the dedicated ICE
>>>   node,
>>> - adds interface clock and power-domain requirements for the ICE node in
>>>   affected DTS files.
>>
>> Konrad/Bjorn, could you please review and let me know for any comments.
> Thanks Konrad for review.
> Bjorn, can you please help in picking patch for v7.3-rc1.

I'm afraid you're unfamiliar with the release process and have
mismatched expectations. The feature development of 7.3 on
maintainer trees is done already and the RCs will only pull in
fixes to the new code.

After v7.3-rc1 is released (and we expect that to happen next
Sunday), for-next branches will be created atop it and maintainers
will be able to accept patches targetting v7.4

Konrad

Re: [PATCH v9 0/2] Enable sdhc inline crypto engine for kodiak and monaco

[Kuldeep Singh]

> I'm afraid you're unfamiliar with the release process and have
> mismatched expectations. The feature development of 7.3 on
> maintainer trees is done already and the RCs will only pull in
> fixes to the new code.

Sure konrad, what I am more afraid here is that patch was in ready to
accept state but somehow got *missed/skipped* to pull in maintainer tree.

I think i was well before that timeline but still couldn't have this
patch in(for v7.3). Not sure if something to change at my end.

Can we atleast pull in for v7.4 now?

-- 
Regards
Kuldeep

Re: [PATCH v9 0/2] Enable sdhc inline crypto engine for kodiak and monaco

[Kuldeep Singh]

On 24-08-2026 15:48, Kuldeep Singh wrote:
>> I'm afraid you're unfamiliar with the release process and have
>> mismatched expectations. The feature development of 7.3 on
>> maintainer trees is done already and the RCs will only pull in
>> fixes to the new code.
> 
> Sure konrad, what I am more afraid here is that patch was in ready to
> accept state but somehow got *missed/skipped* to pull in maintainer tree.
> 
> I think i was well before that timeline but still couldn't have this
> patch in(for v7.3). Not sure if something to change at my end.
> 
> Can we atleast pull in for v7.4 now?
Hi Bjorn,
Can you please help in picking this series for v7.4 if there are no
further comments!!

There's another series[1] dependent on this one which cannot be pulled
unless current one is pulled in.

[1]
https://lore.kernel.org/linux-arm-msm/20260824-enable-ice-clock-scaling-v12-0-09271f583dc6@oss.qualcomm.com/

-- 
Regards
Kuldeep