From: Lizhi Hou <lizhi.hou@amd.com>
To: David Zhang <yidong.zhang@amd.com>, <quic_jhugo@quicinc.com>,
<karol.wachowski@linux.intel.com>, <max.zhen@amd.com>,
<ogabbay@kernel.org>, <dri-devel@lists.freedesktop.org>,
<linux-kernel@vger.kernel.org>
Cc: <sonal.santan@amd.com>, <mario.limonciello@amd.com>
Subject: Re: [PATCH RESEND V1 1/4] accel/amdxdna: Add NPU10 and NPU11 devices
Date: Tue, 10 Nov 2026 10:35:43 -0800 [thread overview]
Message-ID: <19e0180b-5d2a-7af7-cb00-d7d640e64f71@amd.com> (raw)
In-Reply-To: <20261104224302.643329-2-yidong.zhang@amd.com>
On 11/4/26 14:42, David Zhang wrote:
> NPU3 revisions 0x14 and 0x15 are NPU10 and NPU11. Add their classic,
> PF and VF devices with their firmware files and report each by its own
> name. They otherwise use the NPU3 settings.
>
> Signed-off-by: David Zhang <yidong.zhang@amd.com>
> ---
> drivers/accel/amdxdna/amdxdna_pci_drv.c | 14 +++++
> drivers/accel/amdxdna/amdxdna_pci_drv.h | 6 ++
> drivers/accel/amdxdna/npu3_regs.c | 78 +++++++++++++++++++++++++
> 3 files changed, 98 insertions(+)
>
> diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.c b/drivers/accel/amdxdna/amdxdna_pci_drv.c
> index f233eb70a295..685fe1a7dd56 100644
> --- a/drivers/accel/amdxdna/amdxdna_pci_drv.c
> +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.c
> @@ -37,6 +37,14 @@ MODULE_FIRMWARE("amdnpu/17f1_13/npu.sbin");
> MODULE_FIRMWARE("amdnpu/17f1_13/cert.sbin");
> MODULE_FIRMWARE("amdnpu/17f2_13/npu.sbin");
> MODULE_FIRMWARE("amdnpu/17f2_13/cert.sbin");
> +MODULE_FIRMWARE("amdnpu/17f1_14/npu.sbin");
> +MODULE_FIRMWARE("amdnpu/17f1_14/cert.sbin");
> +MODULE_FIRMWARE("amdnpu/17f2_14/npu.sbin");
> +MODULE_FIRMWARE("amdnpu/17f2_14/cert.sbin");
> +MODULE_FIRMWARE("amdnpu/17f1_15/npu.sbin");
> +MODULE_FIRMWARE("amdnpu/17f1_15/cert.sbin");
> +MODULE_FIRMWARE("amdnpu/17f2_15/npu.sbin");
> +MODULE_FIRMWARE("amdnpu/17f2_15/cert.sbin");
>
> /*
> * 0.0: Initial version
> @@ -81,6 +89,12 @@ static const struct amdxdna_device_id amdxdna_ids[] = {
> { 0x17f1, 0x13, &dev_npu3_classic_info },
> { 0x17f2, 0x13, &dev_npu3_pf_info },
> { 0x17f3, 0x13, &dev_npu3_vf_info },
> + { 0x17f1, 0x14, &dev_npu10_classic_info },
> + { 0x17f2, 0x14, &dev_npu10_pf_info },
> + { 0x17f3, 0x14, &dev_npu10_vf_info },
> + { 0x17f1, 0x15, &dev_npu11_classic_info },
> + { 0x17f2, 0x15, &dev_npu11_pf_info },
> + { 0x17f3, 0x15, &dev_npu11_vf_info },
> {0}
> };
>
> diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h
> index 27593190dcf6..5ca32c5b1de0 100644
> --- a/drivers/accel/amdxdna/amdxdna_pci_drv.h
> +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h
> @@ -187,6 +187,12 @@ extern const struct amdxdna_dev_info dev_npu1_info;
> extern const struct amdxdna_dev_info dev_npu3_classic_info;
> extern const struct amdxdna_dev_info dev_npu3_pf_info;
> extern const struct amdxdna_dev_info dev_npu3_vf_info;
> +extern const struct amdxdna_dev_info dev_npu10_classic_info;
> +extern const struct amdxdna_dev_info dev_npu10_pf_info;
> +extern const struct amdxdna_dev_info dev_npu10_vf_info;
> +extern const struct amdxdna_dev_info dev_npu11_classic_info;
> +extern const struct amdxdna_dev_info dev_npu11_pf_info;
> +extern const struct amdxdna_dev_info dev_npu11_vf_info;
> extern const struct amdxdna_dev_info dev_npu4_info;
> extern const struct amdxdna_dev_info dev_npu5_info;
> extern const struct amdxdna_dev_info dev_npu6_info;
> diff --git a/drivers/accel/amdxdna/npu3_regs.c b/drivers/accel/amdxdna/npu3_regs.c
> index cff99ddd3a55..4d38aeaea6d0 100644
> --- a/drivers/accel/amdxdna/npu3_regs.c
> +++ b/drivers/accel/amdxdna/npu3_regs.c
> @@ -197,3 +197,81 @@ const struct amdxdna_dev_info dev_npu3_classic_info = {
> .cert_feature_tbl = npu3_cert_feature_table,
> .ops = &aie4_classic_ops,
> };
> +
> +const struct amdxdna_dev_info dev_npu10_pf_info = {
> + .mbox_bar = NPU3_MBOX_BAR,
> + .sram_bar = NPU3_MBOX_BUFFER_BAR,
> + .psp_bar = NPU3_PSP_BAR_INDEX,
> + .smu_bar = NPU3_SMU_BAR_INDEX,
> + .default_vbnv = "RyzenAI-npu10-pf",
> + .device_type = AMDXDNA_DEV_TYPE_PF,
> + .dev_priv = &npu3_dev_priv,
> + .fw_feature_tbl = npu3_fw_feature_table,
> + .cert_feature_tbl = npu3_cert_feature_table,
> + .ops = &aie4_pf_ops,
> +};
> +
> +const struct amdxdna_dev_info dev_npu10_vf_info = {
> + .mbox_bar = NPU3_MBOX_BAR,
> + .sram_bar = NPU3_MBOX_BUFFER_BAR,
> + .doorbell_bar = NPU3_DOORBELL_BAR,
> + .default_vbnv = "RyzenAI-npu10-vf",
> + .device_type = AMDXDNA_DEV_TYPE_UMQ,
> + .dev_priv = &npu3_dev_vf_priv,
> + .fw_feature_tbl = npu3_fw_feature_table,
> + .cert_feature_tbl = npu3_cert_feature_table,
> + .ops = &aie4_vf_ops,
> +};
> +
> +const struct amdxdna_dev_info dev_npu10_classic_info = {
> + .mbox_bar = NPU3_MBOX_BAR,
> + .sram_bar = NPU3_MBOX_BUFFER_BAR,
> + .psp_bar = NPU3_PSP_BAR_INDEX,
> + .smu_bar = NPU3_SMU_BAR_INDEX,
> + .doorbell_bar = NPU3_DOORBELL_BAR,
> + .default_vbnv = "RyzenAI-npu10",
> + .device_type = AMDXDNA_DEV_TYPE_UMQ,
> + .dev_priv = &npu3_dev_priv,
> + .fw_feature_tbl = npu3_fw_feature_table,
> + .cert_feature_tbl = npu3_cert_feature_table,
> + .ops = &aie4_classic_ops,
> +};
> +
> +const struct amdxdna_dev_info dev_npu11_pf_info = {
> + .mbox_bar = NPU3_MBOX_BAR,
> + .sram_bar = NPU3_MBOX_BUFFER_BAR,
> + .psp_bar = NPU3_PSP_BAR_INDEX,
> + .smu_bar = NPU3_SMU_BAR_INDEX,
> + .default_vbnv = "RyzenAI-npu11-pf",
> + .device_type = AMDXDNA_DEV_TYPE_PF,
> + .dev_priv = &npu3_dev_priv,
> + .fw_feature_tbl = npu3_fw_feature_table,
> + .cert_feature_tbl = npu3_cert_feature_table,
> + .ops = &aie4_pf_ops,
> +};
> +
> +const struct amdxdna_dev_info dev_npu11_vf_info = {
> + .mbox_bar = NPU3_MBOX_BAR,
> + .sram_bar = NPU3_MBOX_BUFFER_BAR,
> + .doorbell_bar = NPU3_DOORBELL_BAR,
> + .default_vbnv = "RyzenAI-npu11-vf",
> + .device_type = AMDXDNA_DEV_TYPE_UMQ,
> + .dev_priv = &npu3_dev_vf_priv,
> + .fw_feature_tbl = npu3_fw_feature_table,
> + .cert_feature_tbl = npu3_cert_feature_table,
> + .ops = &aie4_vf_ops,
> +};
> +
> +const struct amdxdna_dev_info dev_npu11_classic_info = {
> + .mbox_bar = NPU3_MBOX_BAR,
> + .sram_bar = NPU3_MBOX_BUFFER_BAR,
> + .psp_bar = NPU3_PSP_BAR_INDEX,
> + .smu_bar = NPU3_SMU_BAR_INDEX,
> + .doorbell_bar = NPU3_DOORBELL_BAR,
> + .default_vbnv = "RyzenAI-npu11",
> + .device_type = AMDXDNA_DEV_TYPE_UMQ,
> + .dev_priv = &npu3_dev_priv,
> + .fw_feature_tbl = npu3_fw_feature_table,
> + .cert_feature_tbl = npu3_cert_feature_table,
> + .ops = &aie4_classic_ops,
> +};
Reviewed-by: Lizhi Hou <lizhi.hou@amd.com>
next prev parent reply other threads:[~2026-11-10 18:35 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-04 22:42 [PATCH RESEND V1 0/4] accel/amdxdna: Add AIE4 debug buffer support David Zhang
2026-11-04 22:42 ` [PATCH RESEND V1 1/4] accel/amdxdna: Add NPU10 and NPU11 devices David Zhang
2026-11-10 18:35 ` Lizhi Hou [this message]
2026-11-04 22:43 ` [PATCH RESEND V1 2/4] accel/amdxdna: Bump driver version to 1.0 David Zhang
2026-11-10 18:35 ` Lizhi Hou
2026-11-04 22:43 ` [PATCH RESEND V1 3/4] accel/amdxdna: Add AIE4 debug buffer support David Zhang
2026-11-10 18:36 ` Lizhi Hou
2026-11-04 22:43 ` [PATCH RESEND V1 4/4] accel/amdxdna: Add AIE4 CERT firmware version query David Zhang
2026-11-10 18:37 ` Lizhi Hou
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