[PATCH v2 0/4] arm64: dts: qcom: ipq6018: rework CPU Frequency

[PATCH v2 0/4] arm64: dts: qcom: ipq6018: rework CPU Frequency

[Chukun Pan]

Changes in v2:
  Add more CPU Frequencies in ipq6018.dtsi
  Move mp5496 regulator to ipq6018-mp5496.dtsi
  Add LDOA2 regulator to support SDCC voltage scaling

Note that the addition of sdhci node has not been merged yet:
https://lore.kernel.org/lkml/20240306123006.724934-2-amadeus@jmu.edu.cn/

-- 
2.25.1

[PATCH v2 1/4] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency

[Chukun Pan]

Some IPQ6000 SoCs have CPU frequencies up to 1.2GHz,
so add this frequency.

Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
---
 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 4e29adea570a..7fdb119083a2 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -119,6 +119,13 @@ opp-1056000000 {
 			clock-latency-ns = <200000>;
 		};
 
+		opp-1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <850000>;
+			opp-supported-hw = <0x4>;
+			clock-latency-ns = <200000>;
+		};
+
 		opp-1320000000 {
 			opp-hz = /bits/ 64 <1320000000>;
 			opp-microvolt = <862500>;
-- 
2.25.1

Re: [PATCH v2 1/4] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency

[Dmitry Baryshkov]

On Wed, 6 Mar 2024 at 16:04, Chukun Pan <amadeus@jmu.edu.cn> wrote:
>
> Some IPQ6000 SoCs have CPU frequencies up to 1.2GHz,
> so add this frequency.

How is it "some"? You are enabling this opp for all IPQ6000 SoC instances.

>
> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
> ---
>  arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++
>  1 file changed, 7 insertions(+)



-- 
With best wishes
Dmitry

Re: [PATCH v2 1/4] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency

[Chukun Pan]

Hi, Dmitry
> How is it "some"? You are enabling this opp for all IPQ6000 SoC instances.

This is not the case, please see `opp-supported-hw = <0x4>;`.
Also: https://github.com/torvalds/linux/blob/master/drivers/cpufreq/qcom-cpufreq-nvmem.c#L345
This 1.2GHz Frequency only takes effect when BIT(2) exists.
For fused 1.5GHz devices, the 1.2GHz frequency will not appear.
I have tested this patch on both fused 1.2GHz and 1.5GHz devices.

Thanks,
Chukun

-- 
2.25.1

Re: [PATCH v2 1/4] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency

[Dmitry Baryshkov]

On Wed, 6 Mar 2024 at 17:36, Chukun Pan <amadeus@jmu.edu.cn> wrote:
>
> Hi, Dmitry
> > How is it "some"? You are enabling this opp for all IPQ6000 SoC instances.
>
> This is not the case, please see `opp-supported-hw = <0x4>;`.
> Also: https://github.com/torvalds/linux/blob/master/drivers/cpufreq/qcom-cpufreq-nvmem.c#L345
> This 1.2GHz Frequency only takes effect when BIT(2) exists.
> For fused 1.5GHz devices, the 1.2GHz frequency will not appear.
> I have tested this patch on both fused 1.2GHz and 1.5GHz devices.

I did before writing the comment. You have the only IPQ6000 case, it
sets  drv->versions = IPQ6000_VERSION = BIT(2) = 0x4. So, as I said,
you are enabling this for all IPQ6000 SoC versions, unless I miss
something.

-- 
With best wishes
Dmitry

Re: [PATCH v2 1/4] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency

[Chukun Pan]

Hi, Dmitry
> I did before writing the comment. You have the only IPQ6000 case, it
> sets  drv->versions = IPQ6000_VERSION = BIT(2) = 0x4. So, as I said,
> you are enabling this for all IPQ6000 SoC versions, unless I miss
> something.

Sorry, I didn't explain it clearly.
In fact, there are some ipq6000 SoCs whose msm_id is QCOM_ID_IPQ6018.
But the chip screen printing is ipq6000.
OEM boot log: `CPU: IPQ6018, SoC Version: 1.0`
For these SOCs, I tested the frequency is up to 1.5GHz.

Thanks,
Chukun

-- 
2.25.1

Re: [PATCH v2 1/4] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency

[Dmitry Baryshkov]

On Thu, 7 Mar 2024 at 05:02, Chukun Pan <amadeus@jmu.edu.cn> wrote:
>
> Hi, Dmitry
> > I did before writing the comment. You have the only IPQ6000 case, it
> > sets  drv->versions = IPQ6000_VERSION = BIT(2) = 0x4. So, as I said,
> > you are enabling this for all IPQ6000 SoC versions, unless I miss
> > something.
>
> Sorry, I didn't explain it clearly.
> In fact, there are some ipq6000 SoCs whose msm_id is QCOM_ID_IPQ6018.
> But the chip screen printing is ipq6000.
> OEM boot log: `CPU: IPQ6018, SoC Version: 1.0`
> For these SOCs, I tested the frequency is up to 1.5GHz.

So... Do you consider this SoC to be IPQ6018 or IPQ6000?
And anyway, this should be explained in the commit message. Otherwise
anybody reading the commit will have the same questions as I do.

-- 
With best wishes
Dmitry

Re: [PATCH v2 1/4] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency

[Chukun Pan]

Hi, Dmitry
> So... Do you consider this SoC to be IPQ6018 or IPQ6000?

According to the chip silk screen, this is ipq6000. In addition, I have
never seen a board with the SoC chip silk screen printed as ipq6018.

> And anyway, this should be explained in the commit message. Otherwise
> anybody reading the commit will have the same questions as I do.

Sorry, I will explain this in more detail.

Thanks,
Chukun

-- 
2.25.1

Re: [PATCH v2 1/4] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency

[Dmitry Baryshkov]

On Thu, 7 Mar 2024 at 12:02, Chukun Pan <amadeus@jmu.edu.cn> wrote:
>
> Hi, Dmitry
> > So... Do you consider this SoC to be IPQ6018 or IPQ6000?
>
> According to the chip silk screen, this is ipq6000. In addition, I have
> never seen a board with the SoC chip silk screen printed as ipq6018.

Hmm, then what kind of chips do you consider to be ipq6018 if you
haven't seen it on a silkscreen?

>
> > And anyway, this should be explained in the commit message. Otherwise
> > anybody reading the commit will have the same questions as I do.
>
> Sorry, I will explain this in more detail.
>
> Thanks,
> Chukun
>
> --
> 2.25.1
>


-- 
With best wishes
Dmitry

Re: [PATCH v2 1/4] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency

[Kathiravan Thirumoorthy]

On 3/7/2024 8:32 AM, Chukun Pan wrote:
> Hi, Dmitry
>> I did before writing the comment. You have the only IPQ6000 case, it
>> sets  drv->versions = IPQ6000_VERSION = BIT(2) = 0x4. So, as I said,
>> you are enabling this for all IPQ6000 SoC versions, unless I miss
>> something.
> 
> Sorry, I didn't explain it clearly.
> In fact, there are some ipq6000 SoCs whose msm_id is QCOM_ID_IPQ6018.
> But the chip screen printing is ipq6000.
> OEM boot log: `CPU: IPQ6018, SoC Version: 1.0`
> For these SOCs, I tested the frequency is up to 1.5GHz.


Could you share the OEM bootloader log on both these SoCs?


> 
> Thanks,
> Chukun
> 

Re: [PATCH v2 1/4] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency

[Chukun Pan]

> Could you share the OEM bootloader log on both these SoCs?

Chip silk screen: ipq6000, msm_id: ipq6000, bootloader log:

Format: Log Type - Time(microsec) - Message - Optional Info
Log Type: B - Since Boot(Power On Reset),  D - Delta,  S - Statistic
S - QC_IMAGE_VERSION_STRING=BOOT.XF.0.3-00086-IPQ60xxLZB-1
S - IMAGE_VARIANT_STRING=IPQ6018LA
S - OEM_IMAGE_VERSION_STRING=crm-ubuntu200
S - Boot Interface: NAND
S - Secure Boot: Off
S - Boot Config @ 0x000a602c = 0x000002e5
S - JTAG ID @ 0x000a607c = 0x001390e1
S - OEM ID @ 0x000a6080 = 0x00000000
S - Serial Number @ 0x000a4128 = 0xd553f610
S - OEM Config Row 0 @ 0x000a4188 = 0x0000000000000000
S - OEM Config Row 1 @ 0x000a4190 = 0x0000000000000000
S - Feature Config Row 0 @ 0x000a4130 = 0x0000800018200021
S - Feature Config Row 1 @ 0x000a4138 = 0x02c3e83783000009
S - PBL Patch Ver: 1
S - I-cache: On
S - D-cache: On
B -      3413 - PBL, Start
B -       592 - bootable_media_detect_entry, Start
B -      4339 - bootable_media_detect_success, Start
B -      5207 - elf_loader_entry, Start
B -      5380 - auth_hash_seg_entry, Start
B -      7846 - auth_hash_seg_exit, Start
B -      8341 - elf_segs_hash_verify_entry, Start
B -    103774 - elf_segs_hash_verify_exit, Start
B -    107970 - auth_xbl_sec_hash_seg_entry, Start
B -    108114 - auth_xbl_sec_hash_seg_exit, Start
B -    114659 - xbl_sec_segs_hash_verify_entry, Start
B -    114660 - xbl_sec_segs_hash_verify_exit, Start
B -    115589 - PBL, End
B -     97478 - SBL1, Start
B -    237259 - GCC [RstStat:0x0, RstDbg:0x600000] WDog Stat : 0x4
B -    239699 - clock_init, Start
D -      2836 - clock_init, Delta
B -    248270 - boot_flash_init, Start
D -     26962 - boot_flash_init, Delta
B -    278404 - sbl1_ddr_set_default_params, Start
D -       244 - sbl1_ddr_set_default_params, Delta
B -    285022 - boot_config_data_table_init, Start
D -      4788 - boot_config_data_table_init, Delta - (575 Bytes)
B -    294904 - CDT Version:2,Platform ID:8,Major ID:3,Minor ID:2,Subtype:0
B -    299693 - Image Load, Start
D -      6618 - OEM_MISC Image Loaded, Delta - (0 Bytes)
B -    309056 - Image Load, Start
D -      5063 - PMIC Image Loaded, Delta - (0 Bytes)
B -    316925 - sbl1_ddr_set_params, Start
B -    321897 - CPR configuration: 0x555
B -    325099 - Pre_DDR_clock_init, Start
D -       213 - Pre_DDR_clock_init, Delta
D -         0 - sbl1_ddr_set_params, Delta
B -    357856 - Image Load, Start
D -       427 - APDP Image Loaded, Delta - (0 Bytes)
B -    375851 - Image Load, Start
D -       427 - QTI_MISC Image Loaded, Delta - (0 Bytes)
B -    378261 - Image Load, Start
D -       793 - Auth Metadata
D -       641 - Segments hash check
D -     22509 - QSEE Dev Config Image Loaded, Delta - (36362 Bytes)
B -    402722 - Image Load, Start
D -      6863 - Auth Metadata
D -     10309 - Segments hash check
D -    331504 - QSEE Image Loaded, Delta - (1419184 Bytes)
B -    734684 - Image Load, Start
D -       671 - Auth Metadata
D -       945 - Segments hash check
D -     34709 - RPM Image Loaded, Delta - (102800 Bytes)
B -    771070 - Image Load, Start
D -       762 - Auth Metadata
D -      3203 - Segments hash check
D -    124440 - APPSBL Image Loaded, Delta - (563588 Bytes)
B -    911126 - SBL1, End
D -    813953 - SBL1, Delta
S - Flash Throughput, 4000 KB/s  (2122509 Bytes,  432999 us)
S - Core 0 Frequency, 800 MHz
S - DDR Frequency, 466 MHz


U-Boot 2016.01 (Dec 01 2021 - 20:16:45 +0800)

DRAM:  smem ram ptable found: ver: 2 len: 4
512 MiB
NAND:  ONFI device found
ID = 1580a1f8
Vendor = f8
Device = a1
SF: Unsupported flash IDs: manuf 00, jedec 0000, ext_jedec 0000
ipq_spi: SPI Flash not found (bus/cs/speed/mode) = (0/0/48000000/0)
128 MiB
MMC:   <NULL>: 0
PCI0 is not defined in the device tree
In:    serial@78B1000
Out:   serial@78B1000
Err:   serial@78B1000
machid: 8030200


Chip silk screen: ipq6000, msm_id: ipq6018, bootloader log:

Format: Log Type - Time(microsec) - Message - Optional Info
Log Type: B - Since Boot(Power On Reset),  D - Delta,  S - Statistic
S - QC_IMAGE_VERSION_STRING=BOOT.XF.0.3-00077-IPQ60xxLZB-2
S - IMAGE_VARIANT_STRING=IPQ6018LA
S - OEM_IMAGE_VERSION_STRING=crm-ubuntu64
S - Boot Interface: NAND
S - Secure Boot: Off
S - Boot Config @ 0x000a602c = 0x000002e5
S - JTAG ID @ 0x000a607c = 0x001390e1
S - OEM ID @ 0x000a6080 = 0x00000000
S - Serial Number @ 0x000a4128 = 0xcb4a3f56
S - OEM Config Row 0 @ 0x000a4188 = 0x0000000000000000
S - OEM Config Row 1 @ 0x000a4190 = 0x0000000000000000
S - Feature Config Row 0 @ 0x000a4130 = 0x0000800018200021
S - Feature Config Row 1 @ 0x000a4138 = 0x02c3e83783000009
S - PBL Patch Ver: 1
S - I-cache: On
S - D-cache: On
B -      3413 - PBL, Start
B -       592 - bootable_media_detect_entry, Start
B -      4339 - bootable_media_detect_success, Start
B -      5147 - elf_loader_entry, Start
B -      5319 - auth_hash_seg_entry, Start
B -      7785 - auth_hash_seg_exit, Start
B -      8283 - elf_segs_hash_verify_entry, Start
B -    110432 - elf_segs_hash_verify_exit, Start
B -    114856 - auth_xbl_sec_hash_seg_entry, Start
B -    114999 - auth_xbl_sec_hash_seg_exit, Start
B -    121547 - xbl_sec_segs_hash_verify_entry, Start
B -    121548 - xbl_sec_segs_hash_verify_exit, Start
B -    122477 - PBL, End
B -    103273 - SBL1, Start
B -    243359 - GCC [RstStat:0x0, RstDbg:0x600000] WDog Stat : 0x4
B -    245799 - clock_init, Start
D -      2836 - clock_init, Delta
B -    254339 - boot_flash_init, Start
D -     26199 - boot_flash_init, Delta
B -    283772 - sbl1_ddr_set_default_params, Start
D -       213 - sbl1_ddr_set_default_params, Delta
B -    290390 - boot_config_data_table_init, Start
D -      4727 - boot_config_data_table_init, Delta - (575 Bytes)
B -    300242 - CDT Version:2,Platform ID:8,Major ID:3,Minor ID:2,Subtype:0
B -    305091 - Image Load, Start
D -      6618 - OEM_MISC Image Loaded, Delta - (0 Bytes)
B -    314394 - Image Load, Start
D -      5063 - PMIC Image Loaded, Delta - (0 Bytes)
B -    322293 - sbl1_ddr_set_params, Start
B -    327265 - CPR configuration: 0x366
B -    330467 - Pre_DDR_clock_init, Start
D -       183 - Pre_DDR_clock_init, Delta
D -         0 - sbl1_ddr_set_params, Delta
B -    367098 - Image Load, Start
D -       457 - APDP Image Loaded, Delta - (0 Bytes)
B -    380213 - Image Load, Start
D -       458 - QTI_MISC Image Loaded, Delta - (0 Bytes)
B -    382622 - Image Load, Start
D -       824 - Auth Metadata
D -       671 - Segments hash check
D -     22235 - QSEE Dev Config Image Loaded, Delta - (36354 Bytes)
B -    406839 - Image Load, Start
D -      6588 - Auth Metadata
D -     10492 - Segments hash check
D -    329735 - QSEE Image Loaded, Delta - (1470632 Bytes)
B -    737002 - Image Load, Start
D -       671 - Auth Metadata
D -       976 - Segments hash check
D -     34465 - RPM Image Loaded, Delta - (102664 Bytes)
B -    773175 - Image Load, Start
D -       702 - Auth Metadata
D -      3202 - Segments hash check
D -    119011 - APPSBL Image Loaded, Delta - (561320 Bytes)
B -    907802 - SBL1, End
D -    804834 - SBL1, Delta
S - Flash Throughput, 5000 KB/s  (2171545 Bytes,  423057 us)
S - Core 0 Frequency, 800 MHz
S - DDR Frequency, 466 MHz


U-Boot 2016.01 (Mar 18 2020 - 13:15:21 +0800)

DRAM:  smem ram ptable found: ver: 2 len: 4
512 MiB
NAND:  ONFI device found
ID = 1590aac2
Vendor = c2
Device = aa
SF: Unsupported flash IDs: manuf 00, jedec 0000, ext_jedec 0000
ipq_spi: SPI Flash not found (bus/cs/speed/mode) = (0/0/48000000/0)
256 MiB
MMC:   sdhci: Node Not found, skipping initialization

PCI0 is not defined in the device tree
In:    serial@78B1000
Out:   serial@78B1000
Err:   serial@78B1000
machid: 8030200

Re: [PATCH v2 1/4] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency

[Kathiravan Thirumoorthy]

On 3/13/2024 12:48 PM, Chukun Pan wrote:
>> Could you share the OEM bootloader log on both these SoCs?
> 
> Chip silk screen: ipq6000, msm_id: ipq6000, bootloader log:
> 
> Format: Log Type - Time(microsec) - Message - Optional Info
> Log Type: B - Since Boot(Power On Reset),  D - Delta,  S - Statistic
> S - QC_IMAGE_VERSION_STRING=BOOT.XF.0.3-00086-IPQ60xxLZB-1
> S - IMAGE_VARIANT_STRING=IPQ6018LA
> S - OEM_IMAGE_VERSION_STRING=crm-ubuntu200
> S - Boot Interface: NAND
> S - Secure Boot: Off
> S - Boot Config @ 0x000a602c = 0x000002e5
> S - JTAG ID @ 0x000a607c = 0x001390e1

<snip>

> machid: 8030200
> 
> 
> Chip silk screen: ipq6000, msm_id: ipq6018, bootloader log:
> 
> Format: Log Type - Time(microsec) - Message - Optional Info
> Log Type: B - Since Boot(Power On Reset),  D - Delta,  S - Statistic
> S - QC_IMAGE_VERSION_STRING=BOOT.XF.0.3-00077-IPQ60xxLZB-2
> S - IMAGE_VARIANT_STRING=IPQ6018LA
> S - OEM_IMAGE_VERSION_STRING=crm-ubuntu64
> S - Boot Interface: NAND
> S - Secure Boot: Off
> S - Boot Config @ 0x000a602c = 0x000002e5
> S - JTAG ID @ 0x000a607c = 0x001390e1


JTAG ID represents the SKU part number. So this part is also IPQ6000 
only. Not IPQ6018.

SBL build BOOT.XF.0.3-00077-IPQ60xxLZB-2 doesn't have support to 
identify this SKU as IPQ6000. Please check if you can use the latest SBL 
image or the one used in another board (BOOT.XF.0.3-00086-IPQ60xxLZB-1).


> S - OEM ID @ 0x000a6080 = 0x00000000

<snip>

> machid: 8030200

Thanks,

Re: [PATCH v2 1/4] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency

[Konrad Dybcio]

On 3/6/24 15:03, Chukun Pan wrote:
> Some IPQ6000 SoCs have CPU frequencies up to 1.2GHz,

(which ones specifically?)

Konrad
> so add this frequency.
> 
> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
> ---
>   arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++
>   1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> index 4e29adea570a..7fdb119083a2 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -119,6 +119,13 @@ opp-1056000000 {
>   			clock-latency-ns = <200000>;
>   		};
>   
> +		opp-1200000000 {
> +			opp-hz = /bits/ 64 <1200000000>;
> +			opp-microvolt = <850000>;
> +			opp-supported-hw = <0x4>;
> +			clock-latency-ns = <200000>;
> +		};

Looks like said SoC can *only* run the CPUs at 1.2 GHz?

Konrad

Re: [PATCH v2 1/4] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency

[Chukun Pan]

Hi, Konrad
>> Some IPQ6000 SoCs have CPU frequencies up to 1.2GHz,
> (which ones specifically?)

This depends on the efuse value read by the driver.
For the boards I have, there are two cases: fused 1.2GHz
without pmic, fused 1.2GHz and fused 1.5GHz with pmic.

> Looks like said SoC can *only* run the CPUs at 1.2 GHz?

Yes, if the SoC is fused to 1.2GHz.

Thanks,
Chukun

-- 
2.25.1

Re: [PATCH v2 1/4] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency

[Robert Marko]

On 06. 03. 2024. 15:03, Chukun Pan wrote:
> Some IPQ6000 SoCs have CPU frequencies up to 1.2GHz,
> so add this frequency.
>
> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
> ---
>   arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++
>   1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> index 4e29adea570a..7fdb119083a2 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -119,6 +119,13 @@ opp-1056000000 {
>   			clock-latency-ns = <200000>;
>   		};
>   
> +		opp-1200000000 {
> +			opp-hz = /bits/ 64 <1200000000>;
> +			opp-microvolt = <850000>;
Can I ask the source of this voltage level?
Because, its not present in the downstream QCA tree at all.

Regards,
Robert
> +			opp-supported-hw = <0x4>;
> +			clock-latency-ns = <200000>;
> +		};
> +
>   		opp-1320000000 {
>   			opp-hz = /bits/ 64 <1320000000>;
>   			opp-microvolt = <862500>;

Re: [PATCH v2 1/4] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency

[Chukun Pan]

Hi, Robert
> Can I ask the source of this voltage level?
> Because, its not present in the downstream QCA tree at all.

This voltage level is what I guessed through the mhz tool.
The downstream QCA tree uses 0.8625v voltage corresponding
to 1.32GHz, which does not need to be so high.

Thanks,
Chukun

-- 
2.25.1

Re: [PATCH v2 1/4] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency

[Robert Marko]

On Thu, 7 Mar 2024 at 04:26, Chukun Pan <amadeus@jmu.edu.cn> wrote:
>
> Hi, Robert
> > Can I ask the source of this voltage level?
> > Because, its not present in the downstream QCA tree at all.
>
> This voltage level is what I guessed through the mhz tool.
> The downstream QCA tree uses 0.8625v voltage corresponding
> to 1.32GHz, which does not need to be so high.

Well, I am not so sure that it will work for every piece of silicon out there.
In OpenWrt we got bit by fixed voltages on IPQ8074 and had to move to the
downstream CPR driver as the variations between the same family are quite big.

Regards,
Robert
>
> Thanks,
> Chukun
>
> --
> 2.25.1
>

[PATCH v2 2/4] arm64: dts: qcom: ipq6018: add 1.5GHz CPU Frequency

[Chukun Pan]

The IPQ6005 and some IPQ6000 SoCs (with PMIC) have CPU
frequencies up to 1.5GHz, so add this frequency.

Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
---
 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 7fdb119083a2..064b5706a289 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -140,6 +140,13 @@ opp-1440000000 {
 			clock-latency-ns = <200000>;
 		};
 
+		opp-1512000000 {
+			opp-hz = /bits/ 64 <1512000000>;
+			opp-microvolt = <937500>;
+			opp-supported-hw = <0x2>;
+			clock-latency-ns = <200000>;
+		};
+
 		opp-1608000000 {
 			opp-hz = /bits/ 64 <1608000000>;
 			opp-microvolt = <987500>;
-- 
2.25.1

Re: [PATCH v2 2/4] arm64: dts: qcom: ipq6018: add 1.5GHz CPU Frequency

[Dmitry Baryshkov]

On Wed, 6 Mar 2024 at 16:04, Chukun Pan <amadeus@jmu.edu.cn> wrote:
>
> The IPQ6005 and some IPQ6000 SoCs (with PMIC) have CPU
> frequencies up to 1.5GHz, so add this frequency.

After this patch non-PMIC IPQ6000 boardss are broken until patch3 is
applied. Please change the order of these patches.

>
> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
> ---
>  arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> index 7fdb119083a2..064b5706a289 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -140,6 +140,13 @@ opp-1440000000 {
>                         clock-latency-ns = <200000>;
>                 };
>
> +               opp-1512000000 {
> +                       opp-hz = /bits/ 64 <1512000000>;
> +                       opp-microvolt = <937500>;
> +                       opp-supported-hw = <0x2>;
> +                       clock-latency-ns = <200000>;
> +               };
> +
>                 opp-1608000000 {
>                         opp-hz = /bits/ 64 <1608000000>;
>                         opp-microvolt = <987500>;
> --
> 2.25.1
>
>


-- 
With best wishes
Dmitry

Re: [PATCH v2 2/4] arm64: dts: qcom: ipq6018: add 1.5GHz CPU Frequency

[Chukun Pan]

Hi, Dmitry
> After this patch non-PMIC IPQ6000 boardss are broken until patch3 is
> applied. Please change the order of these patches.

This is not the case, please see `opp-supported-hw = <0x2>;`.
Also: https://github.com/torvalds/linux/blob/master/drivers/cpufreq/qcom-cpufreq-nvmem.c#L334
This 1.5GHz Frequency only takes effect when the fuse value is `2'b1`.
I have tested this patch on both fused 1.2GHz and 1.5GHz devices.

Thanks,
Chukun

-- 
2.25.1

Re: [PATCH v2 2/4] arm64: dts: qcom: ipq6018: add 1.5GHz CPU Frequency

[Dmitry Baryshkov]

On Wed, 6 Mar 2024 at 17:40, Chukun Pan <amadeus@jmu.edu.cn> wrote:
>
> Hi, Dmitry
> > After this patch non-PMIC IPQ6000 boardss are broken until patch3 is
> > applied. Please change the order of these patches.
>
> This is not the case, please see `opp-supported-hw = <0x2>;`.
> Also: https://github.com/torvalds/linux/blob/master/drivers/cpufreq/qcom-cpufreq-nvmem.c#L334
> This 1.5GHz Frequency only takes effect when the fuse value is `2'b1`.
> I have tested this patch on both fused 1.2GHz and 1.5GHz devices.

Then the commit message should be changed, because you are enabling
1.5 GHz only for non-IPQ6000 SoCs. This patch has no effect on
IPQ6000.

--
With best wishes
Dmitry

Re: [PATCH v2 1/4] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency

[Chukun Pan]

Hi, Dmitry
> Then the commit message should be changed, because you are enabling
> 1.5 GHz only for non-IPQ6000 SoCs. This patch has no effect on
> IPQ6000.

As I said in another reply, there are some ipq6000 SoCs that will be
recognized by the driver as ipq6018 and fused 1.5GHz.

Thanks,
Chukun

-- 
2.25.1

Re: [PATCH v2 2/4] arm64: dts: qcom: ipq6018: add 1.5GHz CPU Frequency

[Konrad Dybcio]

On 3/6/24 15:03, Chukun Pan wrote:
> The IPQ6005 and some IPQ6000 SoCs (with PMIC) have CPU
> frequencies up to 1.5GHz, so add this frequency.
> 
> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad

[PATCH v2 3/4] arm64: dts: qcom: ipq6018: move mp5496 regulator outside soc dtsi

[Chukun Pan]

Some IPQ60xx SoCs don't have the mp5496 pmic chips. The mp5496
pmic is not part of the ipq60xx SoC, and the mp5496 node is
the same for devices with pmic, so create a common dtsi.

Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
---
 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts |  1 +
 arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 29 ++++++++++++++++++++
 arch/arm64/boot/dts/qcom/ipq6018.dtsi        | 14 ----------
 3 files changed, 30 insertions(+), 14 deletions(-)
 create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi

diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
index f5f4827c0e17..8331890e529e 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
+++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 #include "ipq6018.dtsi"
+#include "ipq6018-mp5496.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1";
diff --git a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
new file mode 100644
index 000000000000..841fd757bee7
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+&rpm_requests {
+	regulators {
+		compatible = "qcom,rpm-mp5496-regulators";
+
+		ipq6018_s2: s2 {
+			regulator-min-microvolt = <725000>;
+			regulator-max-microvolt = <1062500>;
+			regulator-always-on;
+		};
+	};
+};
+
+&CPU0 {
+	cpu-supply = <&ipq6018_s2>;
+};
+
+&CPU1 {
+	cpu-supply = <&ipq6018_s2>;
+};
+
+&CPU2 {
+	cpu-supply = <&ipq6018_s2>;
+};
+
+&CPU3 {
+	cpu-supply = <&ipq6018_s2>;
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 064b5706a289..823b87fdcefd 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -43,7 +43,6 @@ CPU0: cpu@0 {
 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
 			clock-names = "cpu";
 			operating-points-v2 = <&cpu_opp_table>;
-			cpu-supply = <&ipq6018_s2>;
 			#cooling-cells = <2>;
 		};
 
@@ -56,7 +55,6 @@ CPU1: cpu@1 {
 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
 			clock-names = "cpu";
 			operating-points-v2 = <&cpu_opp_table>;
-			cpu-supply = <&ipq6018_s2>;
 			#cooling-cells = <2>;
 		};
 
@@ -69,7 +67,6 @@ CPU2: cpu@2 {
 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
 			clock-names = "cpu";
 			operating-points-v2 = <&cpu_opp_table>;
-			cpu-supply = <&ipq6018_s2>;
 			#cooling-cells = <2>;
 		};
 
@@ -82,7 +79,6 @@ CPU3: cpu@3 {
 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
 			clock-names = "cpu";
 			operating-points-v2 = <&cpu_opp_table>;
-			cpu-supply = <&ipq6018_s2>;
 			#cooling-cells = <2>;
 		};
 
@@ -184,16 +180,6 @@ glink-edge {
 			rpm_requests: rpm-requests {
 				compatible = "qcom,rpm-ipq6018";
 				qcom,glink-channels = "rpm_requests";
-
-				regulators {
-					compatible = "qcom,rpm-mp5496-regulators";
-
-					ipq6018_s2: s2 {
-						regulator-min-microvolt = <725000>;
-						regulator-max-microvolt = <1062500>;
-						regulator-always-on;
-					};
-				};
 			};
 		};
 	};
-- 
2.25.1

Re: [PATCH v2 3/4] arm64: dts: qcom: ipq6018: move mp5496 regulator outside soc dtsi

[Dmitry Baryshkov]

On Wed, 6 Mar 2024 at 16:04, Chukun Pan <amadeus@jmu.edu.cn> wrote:
>
> Some IPQ60xx SoCs don't have the mp5496 pmic chips. The mp5496
> pmic is not part of the ipq60xx SoC, and the mp5496 node is
> the same for devices with pmic, so create a common dtsi.

Please inline this dtsi file into the board file. While it might seem
to make life easier, having such includes makes following regulator
settings much harder. Especially once a board or two start overriding
or expanding those settings.

>
> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
> ---
>  arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts |  1 +
>  arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 29 ++++++++++++++++++++
>  arch/arm64/boot/dts/qcom/ipq6018.dtsi        | 14 ----------
>  3 files changed, 30 insertions(+), 14 deletions(-)
>  create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
> index f5f4827c0e17..8331890e529e 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
> @@ -8,6 +8,7 @@
>  /dts-v1/;
>
>  #include "ipq6018.dtsi"
> +#include "ipq6018-mp5496.dtsi"
>
>  / {
>         model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1";
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
> new file mode 100644
> index 000000000000..841fd757bee7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +
> +&rpm_requests {
> +       regulators {
> +               compatible = "qcom,rpm-mp5496-regulators";
> +
> +               ipq6018_s2: s2 {
> +                       regulator-min-microvolt = <725000>;
> +                       regulator-max-microvolt = <1062500>;
> +                       regulator-always-on;
> +               };
> +       };
> +};
> +
> +&CPU0 {
> +       cpu-supply = <&ipq6018_s2>;
> +};
> +
> +&CPU1 {
> +       cpu-supply = <&ipq6018_s2>;
> +};
> +
> +&CPU2 {
> +       cpu-supply = <&ipq6018_s2>;
> +};
> +
> +&CPU3 {
> +       cpu-supply = <&ipq6018_s2>;
> +};
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> index 064b5706a289..823b87fdcefd 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -43,7 +43,6 @@ CPU0: cpu@0 {
>                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>                         clock-names = "cpu";
>                         operating-points-v2 = <&cpu_opp_table>;
> -                       cpu-supply = <&ipq6018_s2>;
>                         #cooling-cells = <2>;
>                 };
>
> @@ -56,7 +55,6 @@ CPU1: cpu@1 {
>                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>                         clock-names = "cpu";
>                         operating-points-v2 = <&cpu_opp_table>;
> -                       cpu-supply = <&ipq6018_s2>;
>                         #cooling-cells = <2>;
>                 };
>
> @@ -69,7 +67,6 @@ CPU2: cpu@2 {
>                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>                         clock-names = "cpu";
>                         operating-points-v2 = <&cpu_opp_table>;
> -                       cpu-supply = <&ipq6018_s2>;
>                         #cooling-cells = <2>;
>                 };
>
> @@ -82,7 +79,6 @@ CPU3: cpu@3 {
>                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>                         clock-names = "cpu";
>                         operating-points-v2 = <&cpu_opp_table>;
> -                       cpu-supply = <&ipq6018_s2>;
>                         #cooling-cells = <2>;
>                 };
>
> @@ -184,16 +180,6 @@ glink-edge {
>                         rpm_requests: rpm-requests {
>                                 compatible = "qcom,rpm-ipq6018";
>                                 qcom,glink-channels = "rpm_requests";
> -
> -                               regulators {
> -                                       compatible = "qcom,rpm-mp5496-regulators";
> -
> -                                       ipq6018_s2: s2 {
> -                                               regulator-min-microvolt = <725000>;
> -                                               regulator-max-microvolt = <1062500>;
> -                                               regulator-always-on;
> -                                       };
> -                               };
>                         };
>                 };
>         };
> --
> 2.25.1
>
>


-- 
With best wishes
Dmitry

Re: [PATCH v2 3/4] arm64: dts: qcom: ipq6018: move mp5496 regulator outside soc dtsi

[Chukun Pan]

Hi, Dmitry
> Please inline this dtsi file into the board file. While it might seem
> to make life easier, having such includes makes following regulator
> settings much harder. Especially once a board or two start overriding
> or expanding those settings.

Thanks for your suggestion. But unlike mobile phones or dev boards,
I don't think any manufacturer will change the voltage settings of
the mp5496 pmic on the ipq60xx router. The s2 part of mp5496 pmic
is used to supply the CPU, and its min/max voltage corresponds to
the CPU frequency of ipq60xx. Although the downstream qsdk kernel
uses the cpr regulator driver, its min/max voltage is still the
same as the current setting.

Thanks,
Chukun

-- 
2.25.1

[PATCH v2 4/4] arm64: dts: qcom: ipq6018-mp5496: add LDOA2 regulator

[Chukun Pan]

Add LDOA2 regulator of MP5496 to support SDCC voltage scaling.

Suggested-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
---
 arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
index 841fd757bee7..9910bec8a70f 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
@@ -9,9 +9,18 @@ ipq6018_s2: s2 {
 			regulator-max-microvolt = <1062500>;
 			regulator-always-on;
 		};
+
+		ipq6018_l2: l2 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3300000>;
+		};
 	};
 };
 
+&sdhc {
+	vqmmc-supply = <&ipq6018_l2>;
+};
+
 &CPU0 {
 	cpu-supply = <&ipq6018_s2>;
 };
-- 
2.25.1