Re: [PATCH 07/14] clk: renesas: Add support for R9A09G077 SoC

[Paul Barker <paul.barker.ct@bp.renesas.com>]

[-- Attachment #1.1.1: Type: text/plain, Size: 3024 bytes --]

On 29/01/2025 16:37, Thierry Bultel wrote:
> Add the R9A09G077 SoC specific definitions to the CPG driver.
> 
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> ---
>  drivers/clk/renesas/Kconfig         |   5 ++
>  drivers/clk/renesas/Makefile        |   1 +
>  drivers/clk/renesas/r9a09g077-cpg.c | 100 ++++++++++++++++++++++++++++
>  3 files changed, 106 insertions(+)
>  create mode 100644 drivers/clk/renesas/r9a09g077-cpg.c
> 
> diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
> index 7ad59be2099d..017ae990d50c 100644
> --- a/drivers/clk/renesas/Kconfig
> +++ b/drivers/clk/renesas/Kconfig
> @@ -41,6 +41,7 @@ config CLK_RENESAS
>  	select CLK_R9A08G045 if ARCH_R9A08G045
>  	select CLK_R9A09G011 if ARCH_R9A09G011
>  	select CLK_R9A09G057 if ARCH_R9A09G057
> +	select CLK_R9A09G077 if ARCH_R9A09G077
>  	select CLK_SH73A0 if ARCH_SH73A0
>  
>  if CLK_RENESAS
> @@ -198,6 +199,10 @@ config CLK_R9A09G057
>         bool "RZ/V2H(P) clock support" if COMPILE_TEST
>         select CLK_RZV2H
>  
> +config CLK_R9A09G077
> +	bool "RZ/T2H clock support" if COMPILE_TEST
> +	select CLK_RZT2H
> +
>  config CLK_SH73A0
>  	bool "SH-Mobile AG5 clock support" if COMPILE_TEST
>  	select CLK_RENESAS_CPG_MSTP
> diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
> index bd9f0b54fcda..fe11b10bc451 100644
> --- a/drivers/clk/renesas/Makefile
> +++ b/drivers/clk/renesas/Makefile
> @@ -38,6 +38,7 @@ obj-$(CONFIG_CLK_R9A07G054)		+= r9a07g044-cpg.o
>  obj-$(CONFIG_CLK_R9A08G045)		+= r9a08g045-cpg.o
>  obj-$(CONFIG_CLK_R9A09G011)		+= r9a09g011-cpg.o
>  obj-$(CONFIG_CLK_R9A09G057)		+= r9a09g057-cpg.o
> +obj-$(CONFIG_CLK_R9A09G077)		+= r9a09g077-cpg.o
>  obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o
>  
>  # Family
> diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a09g077-cpg.c
> new file mode 100644
> index 000000000000..0b2895c796d1
> --- /dev/null
> +++ b/drivers/clk/renesas/r9a09g077-cpg.c
> @@ -0,0 +1,100 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * r9a09g077 Clock Pulse Generator / Module Standby and Software Reset
> + *
> + * Copyright (C) 2025 Renesas Electronics Corp.
> + *
> + */
> +
> +#include <linux/device.h>
> +#include <linux/clk-provider.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>

Please use alphabetical order for these includes.

> +
> +#include <dt-bindings/clock/r9a09g077-cpg.h>
> +
> +#include "rzt2h-cpg.h"
> +
> +enum clk_ids {
> +	/* Core Clock Outputs exported to DT */
> +	/* External Input Clocks */
> +	LAST_DT_CORE_CLK = R9A09G077_LCDC_CLKD,
> +	CLK_EXTAL,
> +	CLK_LOCO,

I think the above lines have got slightly mixed up, it should be:

    /* Core Clock Outputs exported to DT */
    LAST_DT_CORE_CLK = R9A09G077_LCDC_CLKD,

    /* External Input Clocks */
    CLK_EXTAL,
    CLK_LOCO,

With these minor changes,
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>

-- 
Paul Barker

[-- Attachment #1.1.2: OpenPGP public key --]
[-- Type: application/pgp-keys, Size: 3577 bytes --]

[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 236 bytes --]