From: Akhil P Oommen <quic_akhilpo@quicinc.com>
To: Neil Armstrong <neil.armstrong@linaro.org>,
Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
Konrad Dybcio <konradybcio@kernel.org>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
"Dmitry Baryshkov" <dmitry.baryshkov@linaro.org>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
Bjorn Andersson <andersson@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: <linux-arm-msm@vger.kernel.org>,
<dri-devel@lists.freedesktop.org>,
<freedreno@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>
Subject: Re: [PATCH v4 6/7] arm64: qcom: dts: sm8550: add interconnect and opp-peak-kBps for GPU
Date: Mon, 9 Dec 2024 18:40:33 +0530 [thread overview]
Message-ID: <1af37251-3cdf-47da-8228-2cd5622e1770@quicinc.com> (raw)
In-Reply-To: <e56cd9bf-8fa7-44b0-b00f-45cedb73e194@quicinc.com>
On 12/9/2024 6:32 PM, Akhil P Oommen wrote:
> On 12/5/2024 8:31 PM, Neil Armstrong wrote:
>> Each GPU OPP requires a specific peak DDR bandwidth, let's add
>> those to each OPP and also the related interconnect path.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>
> I haven't checked each bw value, still
>
> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
>
> -Akhil
>
>> ---
>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 +++++++++++++
>> 1 file changed, 13 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> index e7774d32fb6d2288748ecec00bf525b2b3c40fbb..955f58b2cb4e4ca3fd33f1555e36a15cfc82d642 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> @@ -14,6 +14,7 @@
>> #include <dt-bindings/firmware/qcom,scm.h>
>> #include <dt-bindings/gpio/gpio.h>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/interconnect/qcom,icc.h>
>> #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
>> #include <dt-bindings/mailbox/qcom-ipcc.h>
>> #include <dt-bindings/power/qcom-rpmpd.h>
>> @@ -2114,6 +2115,10 @@ gpu: gpu@3d00000 {
>> qcom,gmu = <&gmu>;
>> #cooling-cells = <2>;
>>
>> + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
>> + interconnect-names = "gfx-mem";
>> +
>> status = "disabled";
>>
>> zap-shader {
>> @@ -2127,41 +2132,49 @@ gpu_opp_table: opp-table {
>> opp-680000000 {
>> opp-hz = /bits/ 64 <680000000>;
>> opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
>> + opp-peak-kBps = <16500000>;
>> };
>>
>> opp-615000000 {
>> opp-hz = /bits/ 64 <615000000>;
>> opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
>> + opp-peak-kBps = <16500000>;
Seems like you are using value from "qcom,bus-max" node for each opp in
downstream devicetree. Except for the highest OPP, we should use the
value from "qcom,bus-freq" node. That is supposed to give the best perf
per watt.
-Akhil.
>> };
>>
>> opp-550000000 {
>> opp-hz = /bits/ 64 <550000000>;
>> opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
>> + opp-peak-kBps = <12449218>;
>> };
>>
>> opp-475000000 {
>> opp-hz = /bits/ 64 <475000000>;
>> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
>> + opp-peak-kBps = <8171875>;
>> };
>>
>> opp-401000000 {
>> opp-hz = /bits/ 64 <401000000>;
>> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>> + opp-peak-kBps = <6671875>;
>> };
>>
>> opp-348000000 {
>> opp-hz = /bits/ 64 <348000000>;
>> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
>> + opp-peak-kBps = <6074218>;
>> };
>>
>> opp-295000000 {
>> opp-hz = /bits/ 64 <295000000>;
>> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
>> + opp-peak-kBps = <6074218>;
>> };
>>
>> opp-220000000 {
>> opp-hz = /bits/ 64 <220000000>;
>> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
>> + opp-peak-kBps = <6074218>;
>> };
>> };
>> };
>>
>
next prev parent reply other threads:[~2024-12-09 13:10 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-05 15:01 [PATCH v4 0/7] drm/msm: adreno: add support for DDR bandwidth scaling via GMU Neil Armstrong
2024-12-05 15:01 ` [PATCH v4 1/7] drm/msm: adreno: add defines for gpu & gmu frequency table sizes Neil Armstrong
2024-12-05 15:01 ` [PATCH v4 2/7] drm/msm: adreno: add plumbing to generate bandwidth vote table for GMU Neil Armstrong
2024-12-09 12:07 ` Akhil P Oommen
2024-12-05 15:01 ` [PATCH v4 3/7] drm/msm: adreno: dynamically generate GMU bw table Neil Armstrong
2024-12-09 12:11 ` Akhil P Oommen
2024-12-09 14:06 ` Neil Armstrong
2024-12-05 15:01 ` [PATCH v4 4/7] drm/msm: adreno: find bandwidth index of OPP and set it along freq index Neil Armstrong
2024-12-09 12:28 ` Akhil P Oommen
2024-12-05 15:01 ` [PATCH v4 5/7] drm/msm: adreno: enable GMU bandwidth for A740 and A750 Neil Armstrong
2024-12-09 12:59 ` Akhil P Oommen
2024-12-05 15:01 ` [PATCH v4 6/7] arm64: qcom: dts: sm8550: add interconnect and opp-peak-kBps for GPU Neil Armstrong
2024-12-09 13:02 ` Akhil P Oommen
2024-12-09 13:10 ` Akhil P Oommen [this message]
2024-12-09 14:06 ` Neil Armstrong
2024-12-05 15:01 ` [PATCH v4 7/7] arm64: qcom: dts: sm8650: " Neil Armstrong
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