RE: [PATCH v12 5/9] clk: Add Sunplus SP7021 clock driver

["qinjian[覃健]" <qinjian@cqplus1.com>]

> 
> > > > +       /* This memory region include multi HW regs in discontinuous order.
> > > > +        * clk driver used some discontinuous areas in the memory region.
> > > > +        * Using devm_platform_ioremap_resource() would conflicted with other drivers.
> > > > +        */
> > > > +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > > > +       sp_clk_base = devm_ioremap(dev, res->start, resource_size(res));
> > > > +       if (!sp_clk_base)
> > > > +               return -ENXIO;
> > >
> > > Can you explain this comment in more detail? Generally, the 'reg' properties
> > > of drivers should not overlap, so it is supposed to be safe to call
> > > devm_platform_ioremap_resource() here.
> > >
> > > We discussed this in the context of the iop driver that did have overlapping
> > > registers with this driver, and that was incorrect. Are there any other drivers
> > > that conflict with the clk driver?
> >
> > I means, I must split up the origin reg region into 4 small pieces,
> > and call devm_platform_ioremap_resource() 4 times.
> > Did I should follow this way?
> 
> It depends. What are those other registers, and what drivers use them?
> 
>         Arnd

Include Reset / PinMux / USBC / UPHY regs, which used by related drivers.