* [PATCH net-next v7 01/10] dt-bindings: net: dsa: realtek: add RTL8367S-VB
2026-11-02 14:34 ` [PATCH net-next v7 0/10] net: dsa: realtek: rtl8365mb: add support for RTL8367S-VB Mieczyslaw Nalewaj
@ 2026-11-02 14:36 ` Mieczyslaw Nalewaj
2026-11-02 14:37 ` [PATCH net-next v7 02/10] net: dsa: realtek: rtl8365mb: add chip family infrastructure Mieczyslaw Nalewaj
` (8 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Mieczyslaw Nalewaj @ 2026-11-02 14:36 UTC (permalink / raw)
To: linusw, andrew, olteanv, kuba, davem, edumazet, pabeni, linux,
luizluca, maxime.chevallier, netdev, linux-kernel
The RTL8367S-VB (chip ID 0x6642) is supported by the rtl8365mb driver
with the changes that follow in this series. It is identified by its
chip ID register, so it does not need a compatible string of its own.
List it under realtek,rtl8365mb.
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Reviewed-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
---
Documentation/devicetree/bindings/net/dsa/realtek.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/dsa/realtek.yaml b/Documentation/devicetree/bindings/net/dsa/realtek.yaml
index 473facd..ca775f6 100644
--- a/Documentation/devicetree/bindings/net/dsa/realtek.yaml
+++ b/Documentation/devicetree/bindings/net/dsa/realtek.yaml
@@ -43,7 +43,7 @@ properties:
realtek,rtl8365mb:
Use with models RTL8363NB, RTL8363NB-VB, RTL8363SC, RTL8363SC-VB,
RTL8364NB, RTL8364NB-VB, RTL8365MB, RTL8366SC, RTL8367RB-VB, RTL8367S,
- RTL8367SB, RTL8370MB, RTL8310SR
+ RTL8367S-VB, RTL8367SB, RTL8370MB, RTL8310SR
realtek,rtl8366rb:
Use with models RTL8366RB, RTL8366S
--
2.53.0
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH net-next v7 02/10] net: dsa: realtek: rtl8365mb: add chip family infrastructure
2026-11-02 14:34 ` [PATCH net-next v7 0/10] net: dsa: realtek: rtl8365mb: add support for RTL8367S-VB Mieczyslaw Nalewaj
2026-11-02 14:36 ` [PATCH net-next v7 01/10] dt-bindings: net: dsa: realtek: add RTL8367S-VB Mieczyslaw Nalewaj
@ 2026-11-02 14:37 ` Mieczyslaw Nalewaj
2026-11-02 14:38 ` [PATCH net-next v7 03/10] net: dsa: realtek: rtl8365mb: set speed for family D Mieczyslaw Nalewaj
` (7 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Mieczyslaw Nalewaj @ 2026-11-02 14:37 UTC (permalink / raw)
To: linusw, andrew, olteanv, kuba, davem, edumazet, pabeni, linux,
luizluca, maxime.chevallier, netdev, linux-kernel
Add enum rtl8365mb_family and a family member to struct
rtl8365mb_chip_info, together with rtl8365mb_get_family() declared in a
new rtl8365mb.h so that the VLAN code can use it too. Tag all existing
chips as RTL8365MB_FAMILY_C.
RTL8365MB_FAMILY_D is defined here but no chip uses it yet; it is needed
by the following patches, which add family D handling for chips whose
register layout differs from the existing ones.
No functional change.
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Reviewed-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
---
drivers/net/dsa/realtek/rtl8365mb.h | 14 ++++++++++++++
drivers/net/dsa/realtek/rtl8365mb_main.c | 14 ++++++++++++++
2 files changed, 28 insertions(+)
create mode 100644 drivers/net/dsa/realtek/rtl8365mb.h
diff --git a/drivers/net/dsa/realtek/rtl8365mb.h b/drivers/net/dsa/realtek/rtl8365mb.h
new file mode 100644
index 0000000..315de4c
--- /dev/null
+++ b/drivers/net/dsa/realtek/rtl8365mb.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _RTL8365MB_H
+#define _RTL8365MB_H
+
+#include "realtek.h"
+
+enum rtl8365mb_family {
+ RTL8365MB_FAMILY_C,
+ RTL8365MB_FAMILY_D,
+};
+
+enum rtl8365mb_family rtl8365mb_get_family(struct realtek_priv *priv);
+
+#endif /* _RTL8365MB_H */
diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/realtek/rtl8365mb_main.c
index da06f95..840db5a 100644
--- a/drivers/net/dsa/realtek/rtl8365mb_main.c
+++ b/drivers/net/dsa/realtek/rtl8365mb_main.c
@@ -110,6 +110,7 @@
#include "rtl83xx.h"
#include "rtl8365mb_l2.h"
#include "rtl8365mb_vlan.h"
+#include "rtl8365mb.h"
/* Family-specific data and limits */
#define RTL8365MB_PHYADDRMAX 7
@@ -707,6 +708,7 @@ struct rtl8365mb_extint {
* @name: human-readable chip name
* @chip_id: chip identifier
* @chip_ver: chip silicon revision
+ * @family: chip family
* @extints: available external interfaces
* @jam_table: chip-specific initialization jam table
* @jam_size: size of the chip's jam table
@@ -719,6 +721,7 @@ struct rtl8365mb_chip_info {
const char *name;
u32 chip_id;
u32 chip_ver;
+ enum rtl8365mb_family family;
const struct rtl8365mb_extint extints[RTL8365MB_MAX_NUM_EXTINTS];
const struct rtl8365mb_jam_tbl_entry *jam_table;
size_t jam_size;
@@ -731,6 +734,7 @@ static const struct rtl8365mb_chip_info rtl8365mb_chip_infos[] = {
.name = "RTL8365MB-VC",
.chip_id = 0x6367,
.chip_ver = 0x0040,
+ .family = RTL8365MB_FAMILY_C,
.extints = {
{ 6, 1, PHY_INTF(MII) | PHY_INTF(TMII) |
PHY_INTF(RMII) | PHY_INTF(RGMII) },
@@ -742,6 +746,7 @@ static const struct rtl8365mb_chip_info rtl8365mb_chip_infos[] = {
.name = "RTL8367S",
.chip_id = 0x6367,
.chip_ver = 0x00A0,
+ .family = RTL8365MB_FAMILY_C,
.extints = {
{ 6, 1, PHY_INTF(SGMII) | PHY_INTF(HSGMII) },
{ 7, 2, PHY_INTF(MII) | PHY_INTF(TMII) |
@@ -754,6 +759,7 @@ static const struct rtl8365mb_chip_info rtl8365mb_chip_infos[] = {
.name = "RTL8367SB",
.chip_id = 0x6367,
.chip_ver = 0x0010,
+ .family = RTL8365MB_FAMILY_C,
.extints = {
{ 6, 1, PHY_INTF(MII) | PHY_INTF(TMII) |
PHY_INTF(RMII) | PHY_INTF(RGMII) |
@@ -768,6 +774,7 @@ static const struct rtl8365mb_chip_info rtl8365mb_chip_infos[] = {
.name = "RTL8367RB-VB",
.chip_id = 0x6367,
.chip_ver = 0x0020,
+ .family = RTL8365MB_FAMILY_C,
.extints = {
{ 6, 1, PHY_INTF(MII) | PHY_INTF(TMII) |
PHY_INTF(RMII) | PHY_INTF(RGMII) },
@@ -874,6 +881,13 @@ struct rtl8365mb {
#define pcs_to_rtl8365mb(_pcs) container_of((_pcs), struct rtl8365mb, pcs)
+enum rtl8365mb_family rtl8365mb_get_family(struct realtek_priv *priv)
+{
+ struct rtl8365mb *mb = priv->chip_data;
+
+ return mb->chip_info->family;
+}
+
static int rtl8365mb_phy_poll_busy(struct realtek_priv *priv)
{
u32 val;
--
2.53.0
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH net-next v7 03/10] net: dsa: realtek: rtl8365mb: set speed for family D
2026-11-02 14:34 ` [PATCH net-next v7 0/10] net: dsa: realtek: rtl8365mb: add support for RTL8367S-VB Mieczyslaw Nalewaj
2026-11-02 14:36 ` [PATCH net-next v7 01/10] dt-bindings: net: dsa: realtek: add RTL8367S-VB Mieczyslaw Nalewaj
2026-11-02 14:37 ` [PATCH net-next v7 02/10] net: dsa: realtek: rtl8365mb: add chip family infrastructure Mieczyslaw Nalewaj
@ 2026-11-02 14:38 ` Mieczyslaw Nalewaj
2026-11-02 14:39 ` [PATCH net-next v7 04/10] net: dsa: realtek: rtl8365mb: set RGMII mode " Mieczyslaw Nalewaj
` (6 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Mieczyslaw Nalewaj @ 2026-11-02 14:38 UTC (permalink / raw)
To: linusw, andrew, olteanv, kuba, davem, edumazet, pabeni, linux,
luizluca, maxime.chevallier, netdev, linux-kernel
On family C hardware, forcing a 2.5 Gbps link speed requires relying
strictly on the HSGMII SerDes configuration block, while forcing a dummy
1 Gbps value inside the standard digital interface register. Family D
introduces a dedicated hardware link speed value (5) for 2500M. The speed
bitfield width has been expanded to 3 bits, splitting the most significant
bit into a new separate register field (FORCE_SPEED2), which maps directly
to a distinct per-port digital interface force layout.
On family D the forced-mode configuration (link, duplex, pause, speed)
is written to a per-port register at 0x12c0 + port instead of the
per-extint register. The bit positions of TXPAUSE, RXPAUSE, LINK, DUPLEX
and the low two speed bits are the same as on family C; the upper speed
bits go to bits 13:12 (FORCE_SPEED2), so FORCE_EN (bit 12 on family C)
is not set. A second per-port register at 0x12c8 + port enables the
forced mode: the vendor RTL8367D API writes 0xFFFF there when the MAC
is forced and 0 otherwise. This driver always forces the MAC, as on
family C, so it writes 0xFFFF on every call, including link down.
The family D branch is not reachable until the chip table entry is
added in the last patch.
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
---
drivers/net/dsa/realtek/rtl8365mb_main.c | 82 ++++++++++++++++++++----
1 file changed, 69 insertions(+), 13 deletions(-)
diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/realtek/rtl8365mb_main.c
index 840db5a..2dabc4d 100644
--- a/drivers/net/dsa/realtek/rtl8365mb_main.c
+++ b/drivers/net/dsa/realtek/rtl8365mb_main.c
@@ -344,6 +344,7 @@
#define RTL8365MB_PORT_SPEED_10M 0
#define RTL8365MB_PORT_SPEED_100M 1
#define RTL8365MB_PORT_SPEED_1000M 2
+#define RTL8365MB_D_PORT_SPEED_2500M 5
/* External interface force configuration registers 0~2 */
#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 0x1310 /* EXT0 */
@@ -361,6 +362,28 @@
#define RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK BIT(4)
#define RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK BIT(2)
#define RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK GENMASK(1, 0)
+/* Width of the FORCE_SPEED field, bits[1:0] */
+#define RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_WIDTH 2
+
+/* bits[13:12]; bit 13 reserved, no defined speed value uses it yet */
+#define RTL8365MB_D_DIGITAL_INTERFACE_FORCE_SPEED2_MASK GENMASK(13, 12)
+
+#define RTL8365MB_D_DIGITAL_INTERFACE_FORCE_REG_BASE 0x12c0
+#define RTL8365MB_D_DIGITAL_INTERFACE_FORCE_REG(_port) \
+ (RTL8365MB_D_DIGITAL_INTERFACE_FORCE_REG_BASE + (_port))
+
+#define RTL8365MB_D_DIGITAL_INTERFACE_FORCE_EN_BASE 0x12c8
+#define RTL8365MB_D_DIGITAL_INTERFACE_FORCE_REG_EN(_port) \
+ (RTL8365MB_D_DIGITAL_INTERFACE_FORCE_EN_BASE + (_port))
+
+/* Per-port force-mode enable. The vendor RTL8367D API
+ * (dal_rtl8367d_port_macForceLink_set()) treats it as an on/off switch for
+ * the whole forced configuration: all bits set when the MAC is forced, zero
+ * when it is not. The meaning of the individual bits is not documented.
+ * This driver always forces the MAC, as on family C, so all bits are set
+ * on every call, including link down.
+ */
+#define RTL8365MB_D_DIGITAL_INTERFACE_FORCE_EN_ALL_MASK GENMASK(15, 0)
/* CPU port mask register - controls which ports are treated as CPU ports */
#define RTL8365MB_CPU_PORT_MASK_REG 0x1219
@@ -1646,23 +1669,32 @@ static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port,
u32 r_duplex;
u32 r_speed;
u32 r_link;
+ bool is_d;
int val;
int ret;
if (!extint)
return -ENODEV;
+ is_d = rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D;
if (link) {
/* Force the link up with the desired configuration */
r_link = 1;
r_rx_pause = rx_pause ? 1 : 0;
r_tx_pause = tx_pause ? 1 : 0;
- /* The speed field has no value for 2.5 Gbps: the rate is
- * determined by the HSGMII SerDes configuration, and the
- * vendor driver programs the 1 Gbps value here.
- */
- if (speed == SPEED_2500 || speed == SPEED_1000) {
+ if (speed == SPEED_2500) {
+ if (is_d) {
+ r_speed = RTL8365MB_D_PORT_SPEED_2500M;
+ } else {
+ /* The speed field has no value for 2.5 Gbps:
+ * the rate is determined by the HSGMII SerDes
+ * configuration, and the vendor driver programs
+ * the 1 Gbps value here.
+ */
+ r_speed = RTL8365MB_PORT_SPEED_1000M;
+ }
+ } else if (speed == SPEED_1000) {
r_speed = RTL8365MB_PORT_SPEED_1000M;
} else if (speed == SPEED_100) {
r_speed = RTL8365MB_PORT_SPEED_100M;
@@ -1692,20 +1724,44 @@ static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port,
r_duplex = 0;
}
- val = FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK, 1) |
- FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK,
+ val = FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK,
r_tx_pause) |
FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK,
r_rx_pause) |
FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK, r_link) |
FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK,
r_duplex) |
- FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK, r_speed);
- ret = regmap_write(priv->map,
- RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(extint->id),
- val);
- if (ret)
- return ret;
+ FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK,
+ r_speed &
+ RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK);
+
+ if (is_d) {
+ /* Speed is 3 bits on family D: bits[1:0] go into FORCE_SPEED,
+ * bit[2] goes into FORCE_SPEED2 (bit 12); only 2500M sets it,
+ * bit 13 of the field is unused.
+ */
+ val |= FIELD_PREP(RTL8365MB_D_DIGITAL_INTERFACE_FORCE_SPEED2_MASK,
+ r_speed >>
+ RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_WIDTH);
+ ret = regmap_write(priv->map,
+ RTL8365MB_D_DIGITAL_INTERFACE_FORCE_REG(port),
+ val);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(priv->map,
+ RTL8365MB_D_DIGITAL_INTERFACE_FORCE_REG_EN(port),
+ RTL8365MB_D_DIGITAL_INTERFACE_FORCE_EN_ALL_MASK);
+ if (ret)
+ return ret;
+ } else {
+ val |= FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK, 1);
+ ret = regmap_write(priv->map,
+ RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(extint->id),
+ val);
+ if (ret)
+ return ret;
+ }
return 0;
}
--
2.53.0
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH net-next v7 04/10] net: dsa: realtek: rtl8365mb: set RGMII mode for family D
2026-11-02 14:34 ` [PATCH net-next v7 0/10] net: dsa: realtek: rtl8365mb: add support for RTL8367S-VB Mieczyslaw Nalewaj
` (2 preceding siblings ...)
2026-11-02 14:38 ` [PATCH net-next v7 03/10] net: dsa: realtek: rtl8365mb: set speed for family D Mieczyslaw Nalewaj
@ 2026-11-02 14:39 ` Mieczyslaw Nalewaj
2026-11-02 14:40 ` [PATCH net-next v7 05/10] net: dsa: realtek: rtl8365mb: set and get vlan 4k " Mieczyslaw Nalewaj
` (5 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Mieczyslaw Nalewaj @ 2026-11-02 14:39 UTC (permalink / raw)
To: linusw, andrew, olteanv, kuba, davem, edumazet, pabeni, linux,
luizluca, maxime.chevallier, netdev, linux-kernel
On family D, RGMII on extension interface 1 needs two things that the
other families do not: the EXT1 RGMII TX clock delay field in
EXT_TXC_DLY (0x13f9, bits [5:3]) must be cleared, and the pin mux in
the top-level configuration register must be set up.
The vendor RGMII setup for EXT1 clears the RGMII field of EXT_TXC_DLY
(0x13f9, bits [5:3]) in addition to programming TXDELAY in RGMXF.
Do the same. The init jam table writes 0x0090 to this register, which
leaves the field at 2, so without the clear an extra TX delay would be
applied on top of tx-internal-delay-ps. Clearing it makes
tx-internal-delay-ps the only source of TX delay.
If the internal MAC4 block occupies extension 1, do not advertise RGMII
for port 7 in phylink_get_caps(), so the configuration is refused before
any EXT1 register is touched. This mirrors the vendor RTL8367D API, which
returns an error for RGMII on port 7 when UTP port 4 uses the RGMII
interface. The driver logs a warning naming the conflict. When MAC4 does
not own the pins, bind the RGMII/MII pins to MAC7. SerDes 1, which shares
the pins, is always disabled. The TX delay field, the pin mux and the
SerDes 1 disable are all programmed before RGMII is selected, so the
shared pins are never driven by RGMII and SerDes 1 at the same time.
The family D branch is not reachable until the chip table entry is
added in the last patch.
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
---
drivers/net/dsa/realtek/rtl8365mb_main.c | 72 +++++++++++++++++++++++-
1 file changed, 70 insertions(+), 2 deletions(-)
diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/realtek/rtl8365mb_main.c
index 2dabc4d..d69eed0 100644
--- a/drivers/net/dsa/realtek/rtl8365mb_main.c
+++ b/drivers/net/dsa/realtek/rtl8365mb_main.c
@@ -332,6 +332,12 @@
#define RTL8365MB_SDS_OPTION_ARM_KEY 0x0249
#define RTL8365MB_SDS_OPTION_REG 0x13C1
+#define RTL8365MB_D_SDS_MISC_MODE_FIELD_MASK GENMASK(4, 0)
+/* Shared "disable" encoding for both SDS_MISC's and SDS1_MISC0's
+ * 5-bit mode fields.
+ */
+#define RTL8365MB_D_PORT_SDS_MODE_DISABLE 0x1f
+
/* Embedded DW8051 microcontroller control registers. The microcontroller
* can run firmware to manage the SerDes link, but this driver keeps it in
* reset and disabled: phylink already performs the link management that
@@ -465,6 +471,20 @@
#define RTL8365MB_PORT_MISC_CFG_VLAN_EGRESS_MODE_MASK GENMASK(5, 4)
#define RTL8365MB_PORT_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK GENMASK(3, 0)
+/* EXT_TXC_DLY holds a 3-bit TX clock delay per external interface, for
+ * RGMII ([2:0] EXT0, [5:3] EXT1, [8:6] EXT2) and separately for GMII.
+ * Only the EXT1 RGMII field is used here, and it is cleared in RGMII
+ * mode so that tx-internal-delay-ps is the only TX delay applied.
+ */
+#define RTL8365MB_D_REG_EXT_TXC_DLY 0x13f9
+#define RTL8365MB_D_EXT1_RGMII_TX_DLY_MASK GENMASK(5, 3)
+
+#define RTL8365MB_D_REG_TOP_CON0 0x1d70
+#define RTL8365MB_D_MAC7_SEL_EXT1_MASK BIT(13)
+#define RTL8365MB_D_MAC4_SEL_EXT1_MASK BIT(12)
+
+#define RTL8365MB_D_REG_SDS1_MISC0 0x1d78
+
/**
* enum rtl8365mb_vlan_egress_mode - port VLAN egress mode
* @RTL8365MB_VLAN_EGRESS_MODE_ORIGINAL: follow untag mask in VLAN4k table entry
@@ -1261,6 +1281,33 @@ static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port,
if (ret)
return ret;
+ if (rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D &&
+ extint->id == 1) {
+ ret = regmap_update_bits(priv->map,
+ RTL8365MB_D_REG_EXT_TXC_DLY,
+ RTL8365MB_D_EXT1_RGMII_TX_DLY_MASK, 0);
+ if (ret)
+ return ret;
+
+ /* Bind the RGMII/MII pins to MAC7. MAC4 does not own them:
+ * RGMII is not advertised otherwise, see
+ * rtl8365mb_phylink_get_caps().
+ */
+ ret = regmap_update_bits(priv->map,
+ RTL8365MB_D_REG_TOP_CON0,
+ RTL8365MB_D_MAC7_SEL_EXT1_MASK,
+ RTL8365MB_D_MAC7_SEL_EXT1_MASK);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->map,
+ RTL8365MB_D_REG_SDS1_MISC0,
+ RTL8365MB_D_SDS_MISC_MODE_FIELD_MASK,
+ RTL8365MB_D_PORT_SDS_MODE_DISABLE);
+ if (ret)
+ return ret;
+ }
+
ret = regmap_update_bits(
priv->map, RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(extint->id),
RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(extint->id),
@@ -1773,6 +1820,8 @@ static void rtl8365mb_phylink_get_caps(struct dsa_switch *ds, int port,
rtl8365mb_get_port_extint(ds->priv, port);
struct realtek_priv *priv = ds->priv;
struct rtl8365mb *mb = priv->chip_data;
+ u32 data;
+ int ret;
config->mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
MAC_10 | MAC_100 | MAC_1000FD;
@@ -1802,8 +1851,27 @@ static void rtl8365mb_phylink_get_caps(struct dsa_switch *ds, int port,
* which remain unimplemented.
*/
- if (extint->supported_interfaces & RTL8365MB_PHY_INTERFACE_MODE_RGMII)
- phy_interface_set_rgmii(config->supported_interfaces);
+ if (extint->supported_interfaces & RTL8365MB_PHY_INTERFACE_MODE_RGMII) {
+ /* On family D the EXT1 pins are shared with MAC4 (UTP port 4).
+ * If MAC4 owns them, RGMII on this port cannot work.
+ */
+ if (rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D &&
+ extint->id == 1) {
+ ret = regmap_read(priv->map, RTL8365MB_D_REG_TOP_CON0, &data);
+ if (ret)
+ dev_warn(priv->dev,
+ "failed to read TOP_CON0, RGMII on port %d disabled: %pe\n",
+ port, ERR_PTR(ret));
+ else if (data & RTL8365MB_D_MAC4_SEL_EXT1_MASK)
+ dev_warn(priv->dev,
+ "port %d: EXT1 is owned by MAC4, RGMII disabled\n",
+ port);
+ else
+ phy_interface_set_rgmii(config->supported_interfaces);
+ } else {
+ phy_interface_set_rgmii(config->supported_interfaces);
+ }
+ }
if (extint->supported_interfaces & RTL8365MB_PHY_INTERFACE_MODE_SGMII &&
mb->sds_supported)
--
2.53.0
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH net-next v7 05/10] net: dsa: realtek: rtl8365mb: set and get vlan 4k for family D
2026-11-02 14:34 ` [PATCH net-next v7 0/10] net: dsa: realtek: rtl8365mb: add support for RTL8367S-VB Mieczyslaw Nalewaj
` (3 preceding siblings ...)
2026-11-02 14:39 ` [PATCH net-next v7 04/10] net: dsa: realtek: rtl8365mb: set RGMII mode " Mieczyslaw Nalewaj
@ 2026-11-02 14:40 ` Mieczyslaw Nalewaj
2026-11-02 14:41 ` [PATCH net-next v7 06/10] net: dsa: realtek: rtl8365mb: use raw VID for PVID on " Mieczyslaw Nalewaj
` (4 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Mieczyslaw Nalewaj @ 2026-11-02 14:40 UTC (permalink / raw)
To: linusw, andrew, olteanv, kuba, davem, edumazet, pabeni, linux,
luizluca, maxime.chevallier, netdev, linux-kernel
The hardware structure of 4K VLAN table entries has changed between
silicon families. Family D's CVLAN entry is two 16-bit words rather
than three: there is no third word extending member/untag past bit 7,
and no priority/meter fields at all. The FID field is restricted to a
narrower 2-bit width. The chip itself supports both IVL and SVL.
IVL_EN (bit 3) follows vlan4k->ivl_en, as on family C; the only caller,
rtl8365mb_vlan_4k_port_set(), always requests IVL. SVLAN_CHK_IVL_SVL
(bit 2) is left at 0, as in the vendor RTL8367D CVLAN API, which sets
it only from the SVLAN member API; this driver has no SVLAN support.
vlan4k->ivl_en is read back from IVL_EN.
Reusing the three-word family C layout unconditionally means the third
word is read from and written back to the register that holds it on
family C, but does not exist as a distinct table word on family D's
die; whatever data happens to be there gets folded into member/untag
bits [10:8] on read, and re-written on every read-modify-write cycle
in rtl8365mb_vlan_4k_port_set(). Give family D its own two-word
pack/unpack instead.
The two-word layout matches the vendor switch API for this chip
family, which writes only 0x0510/0x0511 for a CVLAN entry.
The family D paths are not reachable until the RTL8367S-VB chip table
entry is added in the last patch of the series.
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
---
drivers/net/dsa/realtek/rtl8365mb_vlan.c | 161 ++++++++++++++++-------
1 file changed, 111 insertions(+), 50 deletions(-)
diff --git a/drivers/net/dsa/realtek/rtl8365mb_vlan.c b/drivers/net/dsa/realtek/rtl8365mb_vlan.c
index 8d49ffa..36f0d2a 100644
--- a/drivers/net/dsa/realtek/rtl8365mb_vlan.c
+++ b/drivers/net/dsa/realtek/rtl8365mb_vlan.c
@@ -48,12 +48,16 @@
#include "rtl8365mb_vlan.h"
#include "rtl8365mb_table.h"
+#include "rtl8365mb.h"
#include <linux/if_bridge.h>
#include <linux/lockdep.h>
#include <linux/regmap.h>
-/* CVLAN (i.e. VLAN4k) table entry layout, u16[3] */
+/* CVLAN (i.e. VLAN4k) table entry layout: u16[3] on family C, u16[2] on
+ * family D
+ */
#define RTL8365MB_CVLAN_ENTRY_SIZE 3 /* 48-bits */
+#define RTL8365MB_D_CVLAN_ENTRY_SIZE 2 /* 32-bits */
#define RTL8365MB_CVLAN_ENTRY_D0_MBR_MASK GENMASK(7, 0)
#define RTL8365MB_CVLAN_MBR_LO_MASK GENMASK(7, 0)
#define RTL8365MB_CVLAN_ENTRY_D0_UNTAG_MASK GENMASK(15, 8)
@@ -65,6 +69,9 @@
#define RTL8365MB_CVLAN_ENTRY_D1_METERIDX_MASK GENMASK(13, 9)
#define RTL8365MB_CVLAN_METERIDX_LO_MASK GENMASK(4, 0)
#define RTL8365MB_CVLAN_ENTRY_D1_IVL_SVL_MASK GENMASK(14, 14)
+/* Family D CVLAN entry, word 1 (family D has no word 2) */
+#define RTL8365MB_D_CVLAN_ENTRY_D1_IVL_EN_MASK GENMASK(3, 3)
+#define RTL8365MB_D_CVLAN_ENTRY_D1_FID_MASK GENMASK(1, 0)
/* extends RTL8365MB_CVLAN_ENTRY_D0_MBR_MASK */
#define RTL8365MB_CVLAN_ENTRY_D2_MBR_EXT_MASK GENMASK(2, 0)
#define RTL8365MB_CVLAN_MBR_HI_MASK GENMASK(10, 8)
@@ -185,13 +192,16 @@ struct rtl8365mb_vlanmc {
static int rtl8365mb_vlan_4k_read(struct realtek_priv *priv, u16 vid,
struct rtl8365mb_vlan4k *vlan4k)
{
+ bool is_d = rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D;
+ size_t entry_size = is_d ? RTL8365MB_D_CVLAN_ENTRY_SIZE :
+ RTL8365MB_CVLAN_ENTRY_SIZE;
u16 data[RTL8365MB_CVLAN_ENTRY_SIZE];
int val;
int ret;
ret = rtl8365mb_table_query(priv, RTL8365MB_TABLE_CVLAN,
RTL8365MB_TABLE_OP_READ, &vid, 0, 0,
- data, ARRAY_SIZE(data));
+ data, entry_size);
if (ret)
return ret;
@@ -199,33 +209,61 @@ static int rtl8365mb_vlan_4k_read(struct realtek_priv *priv, u16 vid,
memset(vlan4k, 0, sizeof(*vlan4k));
vlan4k->vid = vid;
+ /* member/untag: d0[7:0]/d0[15:8] on both families. Family C
+ * extends these into data[2] bits [2:0]/[5:3] for its 9th-11th
+ * ports; family D's die has only 8 ports and no third table
+ * word, so data[2] does not exist there and must not be read.
+ */
val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D0_MBR_MASK, data[0]);
vlan4k->member = FIELD_PREP(RTL8365MB_CVLAN_MBR_LO_MASK, val);
- val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D2_MBR_EXT_MASK, data[2]);
- vlan4k->member |= FIELD_PREP(RTL8365MB_CVLAN_MBR_HI_MASK, val);
+ if (!is_d) {
+ val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D2_MBR_EXT_MASK, data[2]);
+ vlan4k->member |= FIELD_PREP(RTL8365MB_CVLAN_MBR_HI_MASK, val);
+ }
val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D0_UNTAG_MASK, data[0]);
vlan4k->untag = FIELD_PREP(RTL8365MB_CVLAN_UNTAG_LO_MASK, val);
- val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D2_UNTAG_EXT_MASK, data[2]);
- vlan4k->untag |= FIELD_PREP(RTL8365MB_CVLAN_UNTAG_HI_MASK, val);
-
- vlan4k->fid = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_FID_MASK, data[1]);
- vlan4k->priority_en =
- FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_VBPEN_MASK, data[1]);
- vlan4k->priority =
- FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_VBPRI_MASK, data[1]);
- vlan4k->policing_en =
- FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_ENVLANPOL_MASK, data[1]);
-
- val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_METERIDX_MASK, data[1]);
- val = FIELD_PREP(RTL8365MB_CVLAN_METERIDX_LO_MASK, val);
- vlan4k->meteridx = val;
- val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D2_METERIDX_EXT_MASK, data[2]);
- val = FIELD_PREP(RTL8365MB_CVLAN_METERIDX_HI_MASK, val);
- vlan4k->meteridx |= val;
-
- vlan4k->ivl_en =
- FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_IVL_SVL_MASK, data[1]);
+ if (!is_d) {
+ val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D2_UNTAG_EXT_MASK,
+ data[2]);
+ vlan4k->untag |= FIELD_PREP(RTL8365MB_CVLAN_UNTAG_HI_MASK, val);
+ }
+
+ if (is_d) {
+ vlan4k->fid = FIELD_GET(RTL8365MB_D_CVLAN_ENTRY_D1_FID_MASK,
+ data[1]);
+ /* Family D has no priority/meter fields in this entry -
+ * left zeroed by the memset() above.
+ */
+ vlan4k->ivl_en =
+ FIELD_GET(RTL8365MB_D_CVLAN_ENTRY_D1_IVL_EN_MASK,
+ data[1]);
+ } else {
+ vlan4k->fid = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_FID_MASK,
+ data[1]);
+ vlan4k->priority_en =
+ FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_VBPEN_MASK,
+ data[1]);
+ vlan4k->priority =
+ FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_VBPRI_MASK,
+ data[1]);
+ vlan4k->policing_en =
+ FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_ENVLANPOL_MASK,
+ data[1]);
+
+ val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_METERIDX_MASK,
+ data[1]);
+ val = FIELD_PREP(RTL8365MB_CVLAN_METERIDX_LO_MASK, val);
+ vlan4k->meteridx = val;
+ val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D2_METERIDX_EXT_MASK,
+ data[2]);
+ val = FIELD_PREP(RTL8365MB_CVLAN_METERIDX_HI_MASK, val);
+ vlan4k->meteridx |= val;
+
+ vlan4k->ivl_en =
+ FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_IVL_SVL_MASK,
+ data[1]);
+ }
return 0;
}
@@ -233,6 +271,9 @@ static int rtl8365mb_vlan_4k_read(struct realtek_priv *priv, u16 vid,
static int rtl8365mb_vlan_4k_write(struct realtek_priv *priv,
const struct rtl8365mb_vlan4k *vlan4k)
{
+ bool is_d = rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D;
+ size_t entry_size = is_d ? RTL8365MB_D_CVLAN_ENTRY_SIZE :
+ RTL8365MB_CVLAN_ENTRY_SIZE;
u16 data[RTL8365MB_CVLAN_ENTRY_SIZE] = { 0 };
u16 vid;
int val;
@@ -244,36 +285,56 @@ static int rtl8365mb_vlan_4k_write(struct realtek_priv *priv,
val = FIELD_GET(RTL8365MB_CVLAN_UNTAG_LO_MASK, vlan4k->untag);
data[0] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D0_UNTAG_MASK, val);
- data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_FID_MASK, vlan4k->fid);
- data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_VBPEN_MASK,
- vlan4k->priority_en);
- data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_VBPRI_MASK,
- vlan4k->priority);
- data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_ENVLANPOL_MASK,
- vlan4k->policing_en);
-
- /* FIELD_* does not play nice with struct bitfield. */
- val = vlan4k->meteridx;
- val = FIELD_GET(RTL8365MB_CVLAN_METERIDX_LO_MASK, val);
- data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_METERIDX_MASK, val);
-
- data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_IVL_SVL_MASK,
- vlan4k->ivl_en);
-
- val = FIELD_GET(RTL8365MB_CVLAN_MBR_HI_MASK, vlan4k->member);
- data[2] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D2_MBR_EXT_MASK, val);
-
- val = FIELD_GET(RTL8365MB_CVLAN_UNTAG_HI_MASK, vlan4k->untag);
- data[2] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D2_UNTAG_EXT_MASK, val);
-
- val = vlan4k->meteridx;
- val = FIELD_GET(RTL8365MB_CVLAN_METERIDX_HI_MASK, val);
- data[2] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D2_METERIDX_EXT_MASK, val);
+ if (is_d) {
+ /* IVL_EN follows the caller, as on family C. The vendor CVLAN
+ * API leaves SVLAN_CHK_IVL_SVL at 0, and this driver has no
+ * SVLAN support.
+ */
+ data[1] |= FIELD_PREP(RTL8365MB_D_CVLAN_ENTRY_D1_IVL_EN_MASK,
+ vlan4k->ivl_en);
+ data[1] |= FIELD_PREP(RTL8365MB_D_CVLAN_ENTRY_D1_FID_MASK,
+ vlan4k->fid);
+ /* No priority/meter/member-untag-extension fields exist in
+ * family D's 2-word entry - data[1] and data[0] above are
+ * the whole entry, and data[2] is not part of it at all.
+ */
+ } else {
+ val = vlan4k->fid;
+ data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_FID_MASK, val);
+ data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_VBPEN_MASK,
+ vlan4k->priority_en);
+ data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_VBPRI_MASK,
+ vlan4k->priority);
+ data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_ENVLANPOL_MASK,
+ vlan4k->policing_en);
+
+ /* FIELD_* does not play nice with struct bitfield. */
+ val = vlan4k->meteridx;
+ val = FIELD_GET(RTL8365MB_CVLAN_METERIDX_LO_MASK, val);
+ data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_METERIDX_MASK,
+ val);
+
+ data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_IVL_SVL_MASK,
+ vlan4k->ivl_en);
+
+ val = FIELD_GET(RTL8365MB_CVLAN_MBR_HI_MASK, vlan4k->member);
+ data[2] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D2_MBR_EXT_MASK,
+ val);
+
+ val = FIELD_GET(RTL8365MB_CVLAN_UNTAG_HI_MASK, vlan4k->untag);
+ data[2] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D2_UNTAG_EXT_MASK,
+ val);
+
+ val = vlan4k->meteridx;
+ val = FIELD_GET(RTL8365MB_CVLAN_METERIDX_HI_MASK, val);
+ data[2] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D2_METERIDX_EXT_MASK,
+ val);
+ }
vid = vlan4k->vid;
return rtl8365mb_table_query(priv, RTL8365MB_TABLE_CVLAN,
RTL8365MB_TABLE_OP_WRITE, &vid, 0, 0,
- data, ARRAY_SIZE(data));
+ data, entry_size);
}
static int
--
2.53.0
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH net-next v7 06/10] net: dsa: realtek: rtl8365mb: use raw VID for PVID on family D
2026-11-02 14:34 ` [PATCH net-next v7 0/10] net: dsa: realtek: rtl8365mb: add support for RTL8367S-VB Mieczyslaw Nalewaj
` (4 preceding siblings ...)
2026-11-02 14:40 ` [PATCH net-next v7 05/10] net: dsa: realtek: rtl8365mb: set and get vlan 4k " Mieczyslaw Nalewaj
@ 2026-11-02 14:41 ` Mieczyslaw Nalewaj
2026-11-02 14:42 ` [PATCH net-next v7 07/10] net: dsa: realtek: rtl8365mb: add family D SDS13 PCS support Mieczyslaw Nalewaj
` (3 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Mieczyslaw Nalewaj @ 2026-11-02 14:41 UTC (permalink / raw)
To: linusw, andrew, olteanv, kuba, davem, edumazet, pabeni, linux,
luizluca, maxime.chevallier, netdev, linux-kernel
Family D has no working VLAN member config (MC) table. Its PVID is a
raw 12-bit VID in a per-port register at 0x0700 + port, whereas family C
stores a 5-bit MC table index, two ports per register, at
0x0700 + (port >> 1).
Running the family C code on family D therefore reads an MC table that
does not exist, and writes an MC index into the VID register of port
(port >> 1) instead of the one of the port being configured.
Read the PVID straight from its register in
rtl8365mb_vlan_port_get_pvid(), and make rtl8365mb_vlan_pvid_port_set()
and rtl8365mb_vlan_pvid_port_clear() use direct-VID variants on family D
that skip the MC table. They keep the family C frame filter handling and
rollback on error.
Also clear the family D PVID registers when the VLAN support is set up.
Unlike on family C, where VLANMC index 0 is the neutral PVID, the
register holds a raw VID, and after a reset it keeps its hardware (or
EEPROM) default. Without clearing it an unconfigured port could report
a stale PVID from rtl8365mb_vlan_port_get_pvid(), and
rtl8365mb_port_vlan_filtering() would accept untagged frames into it.
No functional change for family C.
The family D branch is not reachable until the chip table entry is
added in the last patch.
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
---
drivers/net/dsa/realtek/rtl8365mb_main.c | 9 +
drivers/net/dsa/realtek/rtl8365mb_vlan.c | 205 ++++++++++++++++++++++-
drivers/net/dsa/realtek/rtl8365mb_vlan.h | 1 +
3 files changed, 210 insertions(+), 5 deletions(-)
diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/realtek/rtl8365mb_main.c
index d69eed0..e82205c 100644
--- a/drivers/net/dsa/realtek/rtl8365mb_main.c
+++ b/drivers/net/dsa/realtek/rtl8365mb_main.c
@@ -2360,6 +2360,15 @@ static int rtl8365mb_vlan_setup(struct dsa_switch *ds)
int ret;
dsa_switch_for_each_available_port(dp, ds) {
+ /* Start every port with the neutral PVID */
+ ret = rtl8365mb_vlan_port_reset_pvid(priv, dp->index);
+ if (ret) {
+ dev_err(priv->dev,
+ "Failed to reset PVID on port %d\n",
+ dp->index);
+ return ret;
+ }
+
/* Disable vlan-filtering for all ports */
ret = rtl8365mb_port_vlan_filtering(ds, dp->index, false, NULL);
if (ret) {
diff --git a/drivers/net/dsa/realtek/rtl8365mb_vlan.c b/drivers/net/dsa/realtek/rtl8365mb_vlan.c
index 36f0d2a..f44d7ec 100644
--- a/drivers/net/dsa/realtek/rtl8365mb_vlan.c
+++ b/drivers/net/dsa/realtek/rtl8365mb_vlan.c
@@ -44,6 +44,10 @@
*
* VLANMC index 0 is reserved as a neutral PVID, used for standalone ports.
*
+ * Everything above describes chips that have a VLAN membership configuration
+ * table. RTL8365MB_FAMILY_D chips do not have one: their PVID is a raw 12-bit
+ * VID in a per-port register, and no VLANMC entries are allocated.
+ *
*/
#include "rtl8365mb_vlan.h"
@@ -120,6 +124,11 @@
#define RTL8365MB_VLAN_PVID_CTRL_PORT_MCIDX_MASK(_p) \
(0x1F << RTL8365MB_VLAN_PVID_CTRL_PORT_MCIDX_OFFSET(_p))
+#define RTL8365MB_D_VLAN_PVID_CTRL_BASE 0x0700
+#define RTL8365MB_D_VLAN_PVID_CTRL_REG(port) \
+ (RTL8365MB_D_VLAN_PVID_CTRL_BASE + (port))
+#define RTL8365MB_D_VLAN_PVID_CTRL_MASK GENMASK(11, 0)
+
/* Frame type filtering registers */
#define RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_BASE 0x07aa
#define RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_REG(port) \
@@ -171,7 +180,7 @@ struct rtl8365mb_vlan4k {
* This structure is used to get/set entries in the VLAN membership
* configuration database. This feature is largely vestigial, but
* still needed for at least the following features:
- * - PVID configuration
+ * - PVID configuration (family C only, family D has no VLAN MC table)
* - ACL configuration
* - selection of VLAN by the CPU tag when VSEL=1, although the switch
* can also select VLAN based on the VLAN tag if VSEL=0
@@ -740,14 +749,51 @@ int rtl8365mb_vlan_port_get_pvid(struct realtek_priv *priv, int port, u16 *pvid)
u8 vlanmc_idx;
int ret;
- ret = rtl8365mb_vlan_get_pvid_mc(priv, port, &vlanmc_idx, &vlanmc);
- if (ret)
- return ret;
+ if (rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D) {
+ u32 data;
+
+ ret = regmap_read(priv->map,
+ RTL8365MB_D_VLAN_PVID_CTRL_REG(port),
+ &data);
+ if (ret)
+ return ret;
+
+ *pvid = data & RTL8365MB_D_VLAN_PVID_CTRL_MASK;
+ } else {
+ ret = rtl8365mb_vlan_get_pvid_mc(priv, port, &vlanmc_idx,
+ &vlanmc);
+ if (ret)
+ return ret;
+
+ *pvid = vlanmc.evid;
+ }
- *pvid = vlanmc.evid;
return 0;
}
+/**
+ * rtl8365mb_vlan_port_reset_pvid() - Put a port's PVID in its neutral state
+ * @priv: realtek_priv pointer
+ * @port: the port number
+ *
+ * On family C the neutral PVID is VLANMC index 0, which is the reset value, so
+ * there is nothing to do. On family D the PVID is a raw VID in a per-port
+ * register whose value after reset is not defined by the driver (it may come
+ * from the hardware default or from an EEPROM), so clear it to 0.
+ *
+ * Context: Can sleep.
+ * Return: 0 on success, or a negative error code on failure.
+ */
+int rtl8365mb_vlan_port_reset_pvid(struct realtek_priv *priv, int port)
+{
+ if (rtl8365mb_get_family(priv) != RTL8365MB_FAMILY_D)
+ return 0;
+
+ return regmap_update_bits(priv->map,
+ RTL8365MB_D_VLAN_PVID_CTRL_REG(port),
+ RTL8365MB_D_VLAN_PVID_CTRL_MASK, 0);
+}
+
/*
* rtl8365mb_vlan_port_get_framefilter() - Get the ingress frame filtering mode
* for a port
@@ -809,6 +855,68 @@ rtl8365mb_vlan_port_set_framefilter(struct realtek_priv *priv,
val);
}
+/*
+ * rtl8365mb_vlan_pvid_port_set_direct() - Configure a port's PVID as a raw
+ * VID written to its dedicated register, for chip families without a
+ * working VLAN MC table (RTL8365MB_FAMILY_D)
+ *
+ * Reads back the previous PVID and frame filter first so both can be
+ * restored if enabling the new PVID fails partway through, matching
+ * the rollback behavior of the family-C implementation below.
+ *
+ * Context: Can sleep. Must be called with &priv->vlan_lock held.
+ * Return: 0 on success, or a negative error code on failure.
+ */
+static int rtl8365mb_vlan_pvid_port_set_direct(struct realtek_priv *priv,
+ int port, u16 vid)
+{
+ enum rtl8365mb_frame_ingress prev_accepted_frame;
+ u32 prev_pvid;
+ int ret;
+
+ ret = regmap_read(priv->map, RTL8365MB_D_VLAN_PVID_CTRL_REG(port),
+ &prev_pvid);
+ if (ret) {
+ dev_err(priv->dev, "Failed to read current PVID\n");
+ return ret;
+ }
+ prev_pvid &= RTL8365MB_D_VLAN_PVID_CTRL_MASK;
+
+ ret = rtl8365mb_vlan_port_get_framefilter(priv, port,
+ &prev_accepted_frame);
+ if (ret) {
+ dev_err(priv->dev, "Failed to get current framefilter\n");
+ return ret;
+ }
+
+ ret = regmap_update_bits(priv->map,
+ RTL8365MB_D_VLAN_PVID_CTRL_REG(port),
+ RTL8365MB_D_VLAN_PVID_CTRL_MASK,
+ vid & RTL8365MB_D_VLAN_PVID_CTRL_MASK);
+ if (ret) {
+ dev_err(priv->dev, "Failed to set port PVID\n");
+ return ret;
+ }
+
+ /* Changing accept frame is what enables PVID (if not enabled before) */
+ ret = rtl8365mb_vlan_port_set_framefilter(priv, port,
+ RTL8365MB_FRAME_TYPE_ANY_FRAME);
+ if (ret) {
+ dev_err(priv->dev, "Failed to set port frame filter\n");
+ goto undo_pvid_write;
+ }
+
+ return 0;
+
+undo_pvid_write:
+ (void)regmap_update_bits(priv->map,
+ RTL8365MB_D_VLAN_PVID_CTRL_REG(port),
+ RTL8365MB_D_VLAN_PVID_CTRL_MASK, prev_pvid);
+ (void)rtl8365mb_vlan_port_set_framefilter(priv, port,
+ prev_accepted_frame);
+ return ret;
+}
+
/*
* rtl8365mb_vlan_pvid_port_set() - Configure a port's PVID and associated
* VLANMC entry
@@ -821,6 +929,9 @@ rtl8365mb_vlan_port_set_framefilter(struct realtek_priv *priv,
* PVID. Gracefully unwinds and restores previous configuration if a hardware
* write operation fails during execution.
*
+ * On RTL8365MB_FAMILY_D there is no VLANMC table: the VID is written directly
+ * to the port's PVID register and no VLANMC entry is allocated.
+ *
* Context: Can sleep. Must be called with &priv->vlan_lock held.
* Takes and releases &priv->map_lock.
* Return: 0 on success, or a negative error code on failure.
@@ -838,6 +949,13 @@ int rtl8365mb_vlan_pvid_port_set(struct dsa_switch *ds, int port, u16 vid,
lockdep_assert_held(&priv->vlan_lock);
+ /* This chip family has no VLAN MC table - PVID is a raw VID in a
+ * dedicated per-port register, and there is no separate membership
+ * table entry to allocate/track.
+ */
+ if (rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D)
+ return rtl8365mb_vlan_pvid_port_set_direct(priv, port, vid);
+
/* Read the old PVID exclusively to undo in case of error */
ret = rtl8365mb_vlan_get_pvid_mc(priv, port, &prev_vlanmc_idx,
&prev_vlanmc);
@@ -917,6 +1035,77 @@ undo_vlan_mc_port_set:
return ret;
}
+/*
+ * rtl8365mb_vlan_pvid_port_clear_direct() - Remove a port's raw-VID PVID
+ * configuration, for chip families without a working VLAN MC table
+ * (RTL8365MB_FAMILY_D)
+ *
+ * Reads back the previous frame filter first so it can be restored if
+ * clearing the PVID register fails.
+ *
+ * Context: Can sleep. Must be called with &priv->vlan_lock held.
+ * Return: 0 on success, or a negative error code on failure.
+ */
+static int rtl8365mb_vlan_pvid_port_clear_direct(struct dsa_switch *ds,
+ int port, u16 vid)
+{
+ enum rtl8365mb_frame_ingress prev_accepted_frame =
+ RTL8365MB_FRAME_TYPE_ANY_FRAME;
+ struct realtek_priv *priv = ds->priv;
+ bool filtering;
+ u32 cur_pvid;
+ int ret;
+
+ ret = regmap_read(priv->map, RTL8365MB_D_VLAN_PVID_CTRL_REG(port),
+ &cur_pvid);
+ if (ret) {
+ dev_err(priv->dev, "Failed to read current PVID\n");
+ return ret;
+ }
+
+ /* Port is not using this VID as PVID. Nothing to remove. */
+ if ((cur_pvid & RTL8365MB_D_VLAN_PVID_CTRL_MASK) != vid)
+ return 0;
+
+ filtering = dsa_port_is_vlan_filtering(dsa_to_port(ds, port));
+
+ /* Changing accept frame is what really removes PVID. But only do
+ * that if VLAN filtering is enabled.
+ */
+ if (filtering) {
+ ret = rtl8365mb_vlan_port_get_framefilter(priv, port,
+ &prev_accepted_frame);
+ if (ret) {
+ dev_err(priv->dev,
+ "Failed to get current framefilter\n");
+ return ret;
+ }
+
+ ret = rtl8365mb_vlan_port_set_framefilter(
+ priv, port, RTL8365MB_FRAME_TYPE_TAGGED_ONLY);
+ if (ret) {
+ dev_err(priv->dev, "Failed to set port frame filter\n");
+ return ret;
+ }
+ }
+
+ ret = regmap_update_bits(priv->map,
+ RTL8365MB_D_VLAN_PVID_CTRL_REG(port),
+ RTL8365MB_D_VLAN_PVID_CTRL_MASK, 0);
+ if (ret) {
+ dev_err(priv->dev, "Failed to set port PVID to 0\n");
+ goto undo_set_framefilter;
+ }
+
+ return 0;
+
+undo_set_framefilter:
+ if (filtering)
+ (void)rtl8365mb_vlan_port_set_framefilter(priv, port,
+ prev_accepted_frame);
+ return ret;
+}
+
/*
* rtl8365mb_vlan_pvid_port_clear() - Remove a port's PVID configuration
* @ds: dsa switch instance
@@ -926,6 +1115,9 @@ undo_vlan_mc_port_set:
* Resets the target port's hardware PVID allocation to 0. Cleans up and frees
* the associated VLANMC entry if no other ports are referencing it.
*
+ * On RTL8365MB_FAMILY_D the port's PVID register is reset to 0 directly; there
+ * is no VLANMC entry to free.
+ *
* Context: Can sleep. Must be called with &priv->vlan_lock held.
* Takes and releases &priv->map_lock.
* Return: 0 on success, or a negative error code on failure.
@@ -940,6 +1132,9 @@ int rtl8365mb_vlan_pvid_port_clear(struct dsa_switch *ds, int port, u16 vid)
lockdep_assert_held(&priv->vlan_lock);
+ if (rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D)
+ return rtl8365mb_vlan_pvid_port_clear_direct(ds, port, vid);
+
ret = rtl8365mb_vlan_get_pvid_mc(priv, port, &vlanmc_idx,
&vlanmc);
if (ret) {
diff --git a/drivers/net/dsa/realtek/rtl8365mb_vlan.h b/drivers/net/dsa/realtek/rtl8365mb_vlan.h
index 27a526b..9971fb6 100644
--- a/drivers/net/dsa/realtek/rtl8365mb_vlan.h
+++ b/drivers/net/dsa/realtek/rtl8365mb_vlan.h
@@ -20,6 +20,7 @@ enum rtl8365mb_frame_ingress {
int rtl8365mb_vlan_port_get_pvid(struct realtek_priv *priv, int port,
u16 *pvid);
+int rtl8365mb_vlan_port_reset_pvid(struct realtek_priv *priv, int port);
int
rtl8365mb_vlan_port_get_framefilter(struct realtek_priv *priv,
int port,
--
2.53.0
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH net-next v7 07/10] net: dsa: realtek: rtl8365mb: add family D SDS13 PCS support
2026-11-02 14:34 ` [PATCH net-next v7 0/10] net: dsa: realtek: rtl8365mb: add support for RTL8367S-VB Mieczyslaw Nalewaj
` (5 preceding siblings ...)
2026-11-02 14:41 ` [PATCH net-next v7 06/10] net: dsa: realtek: rtl8365mb: use raw VID for PVID on " Mieczyslaw Nalewaj
@ 2026-11-02 14:42 ` Mieczyslaw Nalewaj
2026-11-02 14:43 ` [PATCH net-next v7 08/10] net: dsa: realtek: rtl8365mb: re-latch the family D SerDes Mieczyslaw Nalewaj
` (2 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Mieczyslaw Nalewaj @ 2026-11-02 14:42 UTC (permalink / raw)
To: linusw, andrew, olteanv, kuba, davem, edumazet, pabeni, linux,
luizluca, maxime.chevallier, netdev, linux-kernel
Extend the existing RTL8367S SGMII/HSGMII PCS implementation in this
driver for family D switches, whose CPU SerDes is reached through the
indexed SDS13 window and whose SDS_MISC fields differ from family C.
The register sequence and tuning tables are derived from the GPL-licensed
Realtek RTL8367D port API distributed in the Mercusys MR80X GPL release.
Keep the existing family C path unchanged and select the new behavior from
the driver's chip-family metadata, making the implementation reusable by
other family D boards.
This patch only prepares the family D paths; they become reachable
when the RTL8367S-VB chip entry is added in the last patch.
Co-developed-by: Fabiano Tassotti <fabianotassotti@gmail.com>
Signed-off-by: Fabiano Tassotti <fabianotassotti@gmail.com>
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
---
drivers/net/dsa/realtek/rtl8365mb_main.c | 242 +++++++++++++++++------
1 file changed, 187 insertions(+), 55 deletions(-)
diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/realtek/rtl8365mb_main.c
index e82205c..e297d93 100644
--- a/drivers/net/dsa/realtek/rtl8365mb_main.c
+++ b/drivers/net/dsa/realtek/rtl8365mb_main.c
@@ -262,7 +262,8 @@
* interface, indexed by the external port number with port 5 (the first
* external port) as the base. Other RTL8367 families index this register
* differently (e.g. the RTL8367R uses (id + 1) % 2), so this mapping only
- * holds for the RTL8367C-style parts this driver supports.
+ * holds for the RTL8367C-style parts and for family D, where it is the same
+ * (one bit per external port, base port 5), as in the vendor RTL8367D API.
*/
#define RTL8365MB_BYPASS_LINE_RATE_REG 0x03F7
#define RTL8365MB_BYPASS_LINE_RATE_MASK(_port) BIT((_port) - 5)
@@ -284,6 +285,7 @@
#define RTL8365MB_SDS_INDACS_CMD_BUSY_MASK BIT(8)
#define RTL8365MB_SDS_INDACS_CMD_RUN_MASK BIT(7)
#define RTL8365MB_SDS_INDACS_CMD_WR_MASK BIT(6)
+#define RTL8365MB_SDS_INDACS_CMD_INDEX_MASK GENMASK(5, 0)
#define RTL8365MB_SDS_INDACS_ADR_REG 0x6601
#define RTL8365MB_SDS_INDACS_DATA_REG 0x6602
@@ -313,8 +315,10 @@
#define RTL8365MB_SDS_REG_LINK_STATUS 0x003d
#define RTL8365MB_SDS_LINK_STATUS_LINK_MASK BIT(4)
-/* The embedded SerDes can only be muxed to external interface 1 (MAC8),
- * which is port 6.
+/* On family C the embedded SerDes can only be muxed to external interface
+ * 1 (MAC8), which is port 6. Family D has it on external interface 0
+ * (MAC6), see RTL8365MB_D_SDS_EXT0_INDEX. RTL8365MB_SDS_EXT_INTERFACE_ID
+ * below is the family C id; the SerDes port is 6 on both families.
*/
#define RTL8365MB_SDS_EXT_INTERFACE_ID 1
#define RTL8365MB_SDS_EXT_INTERFACE_PORT 6
@@ -332,7 +336,22 @@
#define RTL8365MB_SDS_OPTION_ARM_KEY 0x0249
#define RTL8365MB_SDS_OPTION_REG 0x13C1
+/* Family D uses the SDS13 indirect window for its MAC6 SerDes. */
+#define RTL8365MB_D_SDS_EXT0_INDEX 13
+#define RTL8365MB_D_FIBER_CFG2_REG 0x13E8
+#define RTL8365MB_D_FIBER_CFG2_RX_DISABLE_MASK GENMASK(7, 6)
+#define RTL8365MB_D_FIBER_CFG2_RX_DISABLE_SDS0 BIT(6)
+#define RTL8365MB_D_SDS_MISC_PA33PC_EN BIT(11)
+#define RTL8365MB_D_SDS_MISC_PA12PC_EN BIT(10)
+#define RTL8365MB_D_SDS_MISC_MAC6_SEL_SDS0 BIT(9)
#define RTL8365MB_D_SDS_MISC_MODE_FIELD_MASK GENMASK(4, 0)
+#define RTL8365MB_D_SDS_MISC_MODE_SGMII 0x02
+#define RTL8365MB_D_SDS_MISC_MODE_HSGMII 0x12
+#define RTL8365MB_D_SDS_MISC_CFG_MASK \
+ (RTL8365MB_D_SDS_MISC_PA33PC_EN | \
+ RTL8365MB_D_SDS_MISC_PA12PC_EN | \
+ RTL8365MB_D_SDS_MISC_MAC6_SEL_SDS0 | \
+ RTL8365MB_D_SDS_MISC_MODE_FIELD_MASK)
/* Shared "disable" encoding for both SDS_MISC's and SDS1_MISC0's
* 5-bit mode fields.
*/
@@ -720,6 +739,21 @@ static const struct rtl8365mb_jam_tbl_entry rtl8365mb_sds_jam_hsgmii[] = {
{ 0x0424, 0xD810 }, { 0x0001, 0x0F80 }, { 0x002E, 0x83F2 },
};
+/* Family D tuning tables from the Realtek vendor port API. */
+static const struct rtl8365mb_jam_tbl_entry rtl8365mb_d_sds_jam_sgmii[] = {
+ { 0x0427, 0x4E0C }, { 0x0428, 0xAA00 }, { 0x0425, 0x5189 },
+ { 0x0424, 0x8414 }, { 0x0423, 0x1020 }, { 0x0410, 0x0002 },
+ { 0x0484, 0x011B }, { 0x0421, 0x8E13 }, { 0x0422, 0x1140 },
+ { 0x0004, 0x074F },
+};
+
+static const struct rtl8365mb_jam_tbl_entry rtl8365mb_d_sds_jam_hsgmii[] = {
+ { 0x0427, 0x4E0C }, { 0x0428, 0xAA00 }, { 0x0425, 0x5189 },
+ { 0x0424, 0x8414 }, { 0x0423, 0x1020 }, { 0x0410, 0x0002 },
+ { 0x0504, 0x051B }, { 0x0421, 0x8E13 }, { 0x0422, 0x1140 },
+ { 0x0004, 0x074F },
+};
+
enum rtl8365mb_phy_interface_mode {
RTL8365MB_PHY_INTERFACE_MODE_INVAL = 0,
RTL8365MB_PHY_INTERFACE_MODE_INTERNAL = BIT(0),
@@ -1320,7 +1354,8 @@ static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port,
return 0;
}
-static int rtl8365mb_sds_write(struct realtek_priv *priv, u16 addr, u16 data)
+static int rtl8365mb_sds_write(struct realtek_priv *priv, u8 index,
+ u16 addr, u16 data)
{
int ret;
@@ -1338,10 +1373,13 @@ static int rtl8365mb_sds_write(struct realtek_priv *priv, u16 addr, u16 data)
*/
return regmap_write(priv->map, RTL8365MB_SDS_INDACS_CMD_REG,
RTL8365MB_SDS_INDACS_CMD_RUN_MASK |
- RTL8365MB_SDS_INDACS_CMD_WR_MASK);
+ RTL8365MB_SDS_INDACS_CMD_WR_MASK |
+ FIELD_PREP(RTL8365MB_SDS_INDACS_CMD_INDEX_MASK,
+ index));
}
-static int rtl8365mb_sds_read(struct realtek_priv *priv, u16 addr, u16 *data)
+static int rtl8365mb_sds_read(struct realtek_priv *priv, u8 index,
+ u16 addr, u16 *data)
{
u32 val;
int ret;
@@ -1351,7 +1389,9 @@ static int rtl8365mb_sds_read(struct realtek_priv *priv, u16 addr, u16 *data)
return ret;
ret = regmap_write(priv->map, RTL8365MB_SDS_INDACS_CMD_REG,
- RTL8365MB_SDS_INDACS_CMD_RUN_MASK);
+ RTL8365MB_SDS_INDACS_CMD_RUN_MASK |
+ FIELD_PREP(RTL8365MB_SDS_INDACS_CMD_INDEX_MASK,
+ index));
if (ret)
return ret;
@@ -1391,6 +1431,14 @@ static int rtl8365mb_sds_probe_option(struct realtek_priv *priv)
int ret;
int i;
+ /* Family D has a fixed SDS13 programming model and does not use the
+ * family C option register to select its tuning table.
+ */
+ if (rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D) {
+ mb->sds_supported = true;
+ return 0;
+ }
+
/* Nothing to probe if no external interface is wired to the SerDes */
for (i = 0; i < RTL8365MB_MAX_NUM_EXTINTS; i++) {
extint = &mb->chip_info->extints[i];
@@ -1472,25 +1520,44 @@ static int rtl8365mb_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
const struct rtl8365mb_jam_tbl_entry *sds_jam;
const int id = RTL8365MB_SDS_EXT_INTERFACE_ID;
struct rtl8365mb *mb = pcs_to_rtl8365mb(pcs);
- struct realtek_priv *priv;
+ struct realtek_priv *priv = mb->priv;
size_t sds_jam_size;
- u32 mode;
+ u32 misc_mask;
+ u32 misc_val;
+ u32 sds_mode;
+ u8 sds_index;
+ bool is_d;
u16 val;
int ret;
int i;
- priv = mb->priv;
+ is_d = rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D;
+ /* Select the appropriate tuning table and SDS mode */
if (interface == PHY_INTERFACE_MODE_2500BASEX) {
- sds_jam = rtl8365mb_sds_jam_hsgmii;
- sds_jam_size = ARRAY_SIZE(rtl8365mb_sds_jam_hsgmii);
- mode = RTL8365MB_EXT_PORT_MODE_HSGMII;
+ if (is_d) {
+ sds_jam = rtl8365mb_d_sds_jam_hsgmii;
+ sds_jam_size = ARRAY_SIZE(rtl8365mb_d_sds_jam_hsgmii);
+ sds_mode = RTL8365MB_D_SDS_MISC_MODE_HSGMII;
+ } else {
+ sds_jam = rtl8365mb_sds_jam_hsgmii;
+ sds_jam_size = ARRAY_SIZE(rtl8365mb_sds_jam_hsgmii);
+ sds_mode = RTL8365MB_EXT_PORT_MODE_HSGMII;
+ }
} else {
- sds_jam = rtl8365mb_sds_jam_sgmii;
- sds_jam_size = ARRAY_SIZE(rtl8365mb_sds_jam_sgmii);
- mode = RTL8365MB_EXT_PORT_MODE_SGMII;
+ if (is_d) {
+ sds_jam = rtl8365mb_d_sds_jam_sgmii;
+ sds_jam_size = ARRAY_SIZE(rtl8365mb_d_sds_jam_sgmii);
+ sds_mode = RTL8365MB_D_SDS_MISC_MODE_SGMII;
+ } else {
+ sds_jam = rtl8365mb_sds_jam_sgmii;
+ sds_jam_size = ARRAY_SIZE(rtl8365mb_sds_jam_sgmii);
+ sds_mode = RTL8365MB_EXT_PORT_MODE_SGMII;
+ }
}
+ sds_index = is_d ? RTL8365MB_D_SDS_EXT0_INDEX : 0;
+
/* Hold the embedded DW8051 microcontroller in reset and keep it
* disabled. The vendor driver loads firmware into it to manage the
* SerDes link, but the firmware only duplicates work that phylink
@@ -1519,34 +1586,57 @@ static int rtl8365mb_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
/* Tune the SerDes with vendor-prescribed parameters */
for (i = 0; i < sds_jam_size; i++) {
- ret = rtl8365mb_sds_write(priv, sds_jam[i].reg,
- sds_jam[i].val);
+ ret = rtl8365mb_sds_write(priv, sds_index,
+ sds_jam[i].reg, sds_jam[i].val);
if (ret)
return ret;
}
- /* Mux the SerDes to MAC8 in the requested mode */
+ /* Family-specific post-tuning configuration */
+ if (is_d) {
+ /* Bit 6 disables the RX of SDS0. As in the vendor RTL8367D
+ * sequence the whole 2-bit field (bits 7:6) is written, so
+ * bit 7 is cleared as well.
+ */
+ ret = regmap_update_bits(priv->map, RTL8365MB_D_FIBER_CFG2_REG,
+ RTL8365MB_D_FIBER_CFG2_RX_DISABLE_MASK,
+ RTL8365MB_D_FIBER_CFG2_RX_DISABLE_SDS0);
+ if (ret)
+ return ret;
+
+ misc_mask = RTL8365MB_D_SDS_MISC_CFG_MASK;
+ misc_val = RTL8365MB_D_SDS_MISC_PA33PC_EN |
+ RTL8365MB_D_SDS_MISC_PA12PC_EN |
+ RTL8365MB_D_SDS_MISC_MAC6_SEL_SDS0 | sds_mode;
+ } else {
+ /* Mux the SerDes to MAC8 in the requested mode */
+ misc_mask = RTL8365MB_SDS_MISC_MAC8_SEL_SGMII_MASK |
+ RTL8365MB_SDS_MISC_MAC8_SEL_HSGMII_MASK;
+ misc_val = (sds_mode == RTL8365MB_EXT_PORT_MODE_SGMII) ?
+ RTL8365MB_SDS_MISC_MAC8_SEL_SGMII_MASK :
+ RTL8365MB_SDS_MISC_MAC8_SEL_HSGMII_MASK;
+ }
+
ret = regmap_update_bits(priv->map, RTL8365MB_SDS_MISC_REG,
- RTL8365MB_SDS_MISC_MAC8_SEL_SGMII_MASK |
- RTL8365MB_SDS_MISC_MAC8_SEL_HSGMII_MASK,
- mode == RTL8365MB_EXT_PORT_MODE_SGMII ?
- RTL8365MB_SDS_MISC_MAC8_SEL_SGMII_MASK :
- RTL8365MB_SDS_MISC_MAC8_SEL_HSGMII_MASK);
+ misc_mask, misc_val);
if (ret)
return ret;
- val = mode << RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(id);
- ret = regmap_update_bits(priv->map,
- RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(id),
- RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(id),
- val);
- if (ret)
- return ret;
+ if (!is_d) {
+ val = sds_mode << RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(id);
+ ret = regmap_update_bits(priv->map,
+ RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(id),
+ RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(id),
+ val);
+ if (ret)
+ return ret;
+ }
/* Take the SerDes out of reset. The vendor driver does this only
* after the SerDes mux and the interface mode are configured.
*/
- ret = rtl8365mb_sds_write(priv, RTL8365MB_SDS_REG_RESET,
+ ret = rtl8365mb_sds_write(priv, sds_index,
+ RTL8365MB_SDS_REG_RESET,
RTL8365MB_SDS_RESET_DEASSERT);
if (ret)
return ret;
@@ -1556,27 +1646,32 @@ static int rtl8365mb_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
* This flushes the FIFOs and ensures a clean state for the link,
* preventing silent drops and CRC errors.
*/
- ret = rtl8365mb_sds_write(priv, RTL8365MB_SDS_REG_BMCR,
+ ret = rtl8365mb_sds_write(priv, sds_index,
+ RTL8365MB_SDS_REG_BMCR,
RTL8365MB_SDS_BMCR_DPRST_PHASE1);
if (ret)
return ret;
- ret = rtl8365mb_sds_write(priv, RTL8365MB_SDS_REG_BMCR,
+ ret = rtl8365mb_sds_write(priv, sds_index,
+ RTL8365MB_SDS_REG_BMCR,
RTL8365MB_SDS_BMCR_DPRST_PHASE2);
if (ret)
return ret;
/* Keep SGMII in-band autonegotiation disabled: the link parameters are
- * forced from rtl8365mb_pcs_link_up() instead.
+ * forced from rtl8365mb_pcs_link_up() instead (family C), or from
+ * mac_link_up() (family D).
*/
- ret = rtl8365mb_sds_read(priv, RTL8365MB_SDS_REG_NWAY, &val);
+ ret = rtl8365mb_sds_read(priv, sds_index,
+ RTL8365MB_SDS_REG_NWAY, &val);
if (ret)
return ret;
val &= ~RTL8365MB_SDS_NWAY_EN_MASK;
val |= RTL8365MB_SDS_NWAY_RESTART_MASK;
- return rtl8365mb_sds_write(priv, RTL8365MB_SDS_REG_NWAY, val);
+ return rtl8365mb_sds_write(priv, sds_index,
+ RTL8365MB_SDS_REG_NWAY, val);
}
static bool rtl8365mb_interface_is_serdes(phy_interface_t interface)
@@ -1601,18 +1696,27 @@ static void rtl8365mb_pcs_get_state(struct phylink_pcs *pcs,
{
struct rtl8365mb *mb = pcs_to_rtl8365mb(pcs);
struct realtek_priv *priv = mb->priv;
+ u8 sds_index = 0;
u16 status;
+ bool is_d;
u32 val;
int ret;
- /* In-band autonegotiation is not implemented, so the link parameters are
- * forced from rtl8365mb_pcs_link_up(). The real link state must still be
- * read from the SerDes itself: the embedded DW8051 microcontroller that
+ is_d = rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D;
+
+ /* In-band autonegotiation is not implemented, so the link parameters
+ * are forced from rtl8365mb_pcs_link_up() on family C, and from
+ * mac_link_up() on family D. The real link state must still be read
+ * from the SerDes itself: the embedded DW8051 microcontroller that
* the vendor firmware uses to poll the SerDes is kept disabled (see
* rtl8365mb_pcs_config()), so the link status register can be read
* directly through the SDS_INDACS window without racing the auto-poll.
*/
- ret = rtl8365mb_sds_read(priv, RTL8365MB_SDS_REG_LINK_STATUS, &status);
+ if (is_d)
+ sds_index = RTL8365MB_D_SDS_EXT0_INDEX;
+
+ ret = rtl8365mb_sds_read(priv, sds_index,
+ RTL8365MB_SDS_REG_LINK_STATUS, &status);
if (ret) {
state->link = false;
return;
@@ -1623,6 +1727,23 @@ static void rtl8365mb_pcs_get_state(struct phylink_pcs *pcs,
if (!state->link)
return;
+ if (is_d) {
+ if (state->interface == PHY_INTERFACE_MODE_2500BASEX) {
+ state->duplex = DUPLEX_FULL;
+ state->speed = SPEED_2500;
+ } else {
+ /* Keep what phylink passed in, but never report the
+ * link up with an unknown speed: mac_link_up() cannot
+ * force the port with it.
+ */
+ if (state->speed == SPEED_UNKNOWN)
+ state->speed = SPEED_1000;
+ if (state->duplex == DUPLEX_UNKNOWN)
+ state->duplex = DUPLEX_FULL;
+ }
+ return;
+ }
+
/* The speed and duplex are forced; read them back from the values
* programmed into the SerDes MISC register.
*/
@@ -1664,6 +1785,12 @@ static void rtl8365mb_pcs_link_up(struct phylink_pcs *pcs,
u32 r_speed;
int ret;
+ /* Family D forces the external MAC ability from mac_link_up(); its
+ * SDS_MISC fields do not share the family C link-force layout.
+ */
+ if (rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D)
+ return;
+
/* The speed field has no value for 2.5 Gbps: the rate is determined by
* the HSGMII SerDes configuration, and the vendor driver programs the
* 1 Gbps value here.
@@ -1954,7 +2081,7 @@ static void rtl8365mb_phylink_mac_link_down(struct phylink_config *config,
/* phylink has no pcs_link_down callback, so on the SerDes path only the
* MAC external interface force is reset here. Clearing the MAC force is
* enough to bring the link down; the SerDes keeps presenting its last
- * forced state until the next pcs_link_up() reprograms it.
+ * forced state (family C) until the next pcs_link_up() reprograms it.
*/
if (phy_interface_mode_is_rgmii(interface) ||
rtl8365mb_interface_is_serdes(interface)) {
@@ -1987,9 +2114,11 @@ static void rtl8365mb_phylink_mac_link_up(struct phylink_config *config,
p = &mb->ports[port];
schedule_delayed_work(&p->mib_work, 0);
- /* The SerDes forced link state is programmed by the PCS in
+ /* On family C the SerDes forced link state is programmed by the PCS in
* rtl8365mb_pcs_link_up(); here only the MAC external interface force
- * is configured, for both RGMII and SerDes.
+ * is configured. On family D pcs_link_up() does nothing, and the MAC
+ * external interface force is the only forced link state, for both
+ * RGMII and SerDes.
*/
if (phy_interface_mode_is_rgmii(interface) ||
rtl8365mb_interface_is_serdes(interface)) {
@@ -2003,18 +2132,21 @@ static void rtl8365mb_phylink_mac_link_up(struct phylink_config *config,
return;
}
- /* The SerDes has its own pause enables; program them from
- * the resolved pause modes, as the vendor driver does when
- * forcing the link on a SerDes external interface. These
- * bits, not the MAC force pause bits, gate pause on the
- * SerDes external interface: flow control testing shows
- * that pause frames are only emitted with the SerDes TXFC
- * bit set, while the MAC force pause bits alone have no
- * effect on this port. This is done here rather than in
- * rtl8365mb_pcs_link_up() because pcs_link_up() carries no
- * pause information.
+ /* Family C: the SerDes has its own pause enables; program
+ * them from the resolved pause modes, as the vendor driver
+ * does when forcing the link on a SerDes external
+ * interface. These bits, not the MAC force pause bits, gate
+ * pause on the SerDes external interface: flow control
+ * testing shows that pause frames are only emitted with the
+ * SerDes TXFC bit set, while the MAC force pause bits alone
+ * have no effect on this port. This is done here rather
+ * than in rtl8365mb_pcs_link_up() because pcs_link_up()
+ * carries no pause information. Family D does not use this
+ * path: its pause bits are set in the forced-mode register
+ * by rtl8365mb_ext_config_forcemode().
*/
- if (rtl8365mb_interface_is_serdes(interface)) {
+ if (rtl8365mb_interface_is_serdes(interface) &&
+ rtl8365mb_get_family(priv) != RTL8365MB_FAMILY_D) {
u32 val = 0;
if (tx_pause)
--
2.53.0
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH net-next v7 08/10] net: dsa: realtek: rtl8365mb: re-latch the family D SerDes
2026-11-02 14:34 ` [PATCH net-next v7 0/10] net: dsa: realtek: rtl8365mb: add support for RTL8367S-VB Mieczyslaw Nalewaj
` (6 preceding siblings ...)
2026-11-02 14:42 ` [PATCH net-next v7 07/10] net: dsa: realtek: rtl8365mb: add family D SDS13 PCS support Mieczyslaw Nalewaj
@ 2026-11-02 14:43 ` Mieczyslaw Nalewaj
2026-11-02 14:44 ` [PATCH net-next v7 09/10] net: dsa: realtek: rtl8365mb: make L2/LUT access work on family D Mieczyslaw Nalewaj
2026-11-02 14:45 ` [PATCH net-next v7 10/10] net: dsa: realtek: rtl8365mb: add support for RTL8367S-VB Mieczyslaw Nalewaj
9 siblings, 0 replies; 11+ messages in thread
From: Mieczyslaw Nalewaj @ 2026-11-02 14:43 UTC (permalink / raw)
To: linusw, andrew, olteanv, kuba, davem, edumazet, pabeni, linux,
luizluca, maxime.chevallier, netdev, linux-kernel
The family D receiver latches on the DISABLE -> HSGMII edge in SDS_MISC
rather than on the value, and it will not latch until the MAC at the
other end of the trunk has brought its own half of the link up. If it
does not latch, the trunk reports 2.5Gbps/Full on both sides but moves
no frames: the CPU MAC transmits, the switch CPU port counts no octets,
and there are no CRC, alignment or FIFO errors.
The two ends can be seconds apart, e.g. on an IPQ5018 board:
5.27 rtl8365mb: configuring for fixed/2500base-x <- pcs_config()
7.72 ipq5018-gmac-dwmac eth0: configuring for fixed/2500base-x
8.02 ipq5018-gmac-dwmac eth0: Link is Up - 2.5Gbps/Full
8.56 SerDes latches
pcs_config() runs seconds before the far-end MAC even starts
configuring, so a single edge driven from there is not enough: the
receiver has nothing to latch onto yet. Neither is pcs_link_up(),
which is seconds early for the same reason. phylink does not help
either - it never calls rtl8365mb_pcs_get_state() for this port in
the first place, since mb->pcs.poll only arms phylink's own poll for
in-band links, and this CPU port is a fixed link.
There is no local signal that predicts when the far-end MAC will
bring up its half of the link (bit 8 of the SDS link-status word
does not change ahead of it), so the work cannot wait for it; it can
only tell afterwards, from the link-status bit, whether an edge took.
The far-end MAC starts when its conduit is brought up, which DSA
reports through ->conduit_state_change(), so an episode of re-latch
attempts starts there. Only the conduit of the CPU port that carries
the SerDes (port 6) is considered: the chip can have a second CPU
port on RGMII, and its conduit says nothing about the SerDes link.
pcs_config() only arms the work, and starts an episode itself if that
conduit is already up. The work re-arms itself after each edge; the
next run checks whether the edge took, rather than waiting on a poll
that will not come. When the conduit goes down the work is stopped, so
a link without a far end is not reported as lost and not parked every
10 s.
Each attempt (park for 20 ms, then restore the target mode) is
performed by a work item rather than from the callbacks, because the
attempts have to continue for seconds after they have returned.
pcs_config(), pcs_disable(), teardown() and conduit_state_change() are
serialized by a new sds_cfg_lock and cancel the work before touching
SDS_MISC or restarting it, so an attempt never interleaves with a
reconfiguration. Before parking, the work reads the link status itself
and does not park if the receiver has already latched, since the
condition that queued it may be stale by the time it runs; it then ends
the episode instead.
Attempts are spaced about 1 s apart and capped at
RTL8365MB_D_SDS_RELATCH_MAX_TRIES (15) per fast episode. After the last
attempt one more run checks whether it took and only then warns that
the SerDes did not latch. The work then keeps driving one edge per
RTL8365MB_D_SDS_HEALTHCHECK_INTERVAL, so a far end that comes up late
or a link that drops again is recovered without a reconfiguration,
at a bounded cost of one 20 ms park per interval.
Once the receiver has latched, the work keeps checking the link every
10 s (RTL8365MB_D_SDS_HEALTHCHECK_INTERVAL). If it finds the link down
outside a reconfiguration, e.g. after the far end reset its PLL, it
logs that and starts a new episode.
For family D, pcs_config() keeps the masked update of SDS_MISC and saves
the value it wrote as the target the work restores. The work parks and
restores with masked updates over the same fields, so other bits are
never touched.
The work reads the SerDes link status through the SDS_INDACS indirect
access window, a multi-register ADR/CMD/DATA sequence that the PCS
callbacks also use, so those sequences are serialized by a new sds_lock.
The SDS_MISC updates need no extra locking: each one is a single regmap
read-modify-write.
The work is only armed for 2500base-x, the mode the re-latch edge was
observed with. It is cancelled from pcs_disable(), from pcs_config()
before SDS_MISC is touched, from conduit_state_change() and from
teardown(), and disabled by a reboot notifier and by a devres action.
disable_delayed_work_sync() is used in the latter two so that a late
pcs_config() cannot queue the work again, and so that it never outlives
the PCS or the driver data and does not touch the bus while it is shut
down. dsa_switch_shutdown() does not stop the PCS, which is why the
reboot notifier is needed.
If restoring the target mode fails, the lane stays parked. The mode
field in SDS_MISC tells so, and the next run of the work puts it back
before doing anything else. If the work is stopped before that run, the
lane stays parked until the next pcs_config().
No chip uses family D before the last patch of the series, so this code
is unreachable until then.
Co-developed-by: Oleg Gavrilov <gabonpivovich@gmail.com>
Signed-off-by: Oleg Gavrilov <gabonpivovich@gmail.com>
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
---
drivers/net/dsa/realtek/rtl8365mb_main.c | 387 ++++++++++++++++++++++-
1 file changed, 372 insertions(+), 15 deletions(-)
diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/realtek/rtl8365mb_main.c
index e297d93..4937ffc 100644
--- a/drivers/net/dsa/realtek/rtl8365mb_main.c
+++ b/drivers/net/dsa/realtek/rtl8365mb_main.c
@@ -97,6 +97,9 @@
#include <linux/irqdomain.h>
#include <linux/mii.h>
#include <linux/mutex.h>
+#include <linux/workqueue.h>
+#include <linux/reboot.h>
+#include <linux/cleanup.h>
#include <linux/of_irq.h>
#include <linux/regmap.h>
#include <linux/if_bridge.h>
@@ -299,6 +302,29 @@
#define RTL8365MB_SDS_MISC_SGMII_SPD_MASK GENMASK(8, 7)
#define RTL8365MB_SDS_MISC_MAC8_SEL_SGMII_MASK BIT(6)
+/* Re-latch retry interval and attempt budget. Each attempt parks the
+ * SerDes for 20 ms, so a far end that never comes up must not be retried
+ * at this rate forever, and the interval must not be so tight that
+ * back-to-back parks starve a link that is about to latch. The count is
+ * reset to 1 whenever an episode starts and to 0 whenever the receiver
+ * latches. Episodes start when the conduit comes up, so with the
+ * interval below the budget is roughly RELATCH_MAX_TRIES seconds, which
+ * is generous for a far end that needs a moment to bring up its half of
+ * the link.
+ */
+#define RTL8365MB_D_SDS_RELATCH_INTERVAL (HZ)
+#define RTL8365MB_D_SDS_RELATCH_MAX_TRIES 15
+
+/* The SerDes stays parked until the restore write succeeds, so the write is
+ * attempted up to this many times before giving up until the next run.
+ */
+#define RTL8365MB_D_SDS_RESTORE_TRIES 3
+
+/* How often a latched (or out-of-budget) SerDes is checked, and re-latched
+ * if still down. Much slower than the re-latch interval.
+ */
+#define RTL8365MB_D_SDS_HEALTHCHECK_INTERVAL (10 * HZ)
+
/* SerDes internal registers, accessed via the SDS_INDACS registers. The BMCR
* data path reset holds BMCR_ANENABLE | BMCR_ISOLATE while toggling the
* vendor-specific low bits from phase 1 to phase 2, which triggers a data path
@@ -938,10 +964,23 @@ struct rtl8365mb_port {
* @chip_info: chip-specific info about the attached switch
* @cpu: CPU tagging and CPU port configuration for this chip
* @mib_lock: prevent concurrent reads of MIB counters
+ * @sds_cfg_lock: serializes pcs_config(), pcs_disable(), teardown() and
+ * conduit_state_change(), which arm, start and stop the
+ * re-latch work
+ * @sds_lock: serializes access to the shared SDS_INDACS ADR/CMD/DATA window,
+ * reachable both from phylink's PCS callbacks and from the
+ * family D SerDes re-latch work
* @ports: per-port data
* @pcs: PCS for the SerDes external interface
* @sds_supported: SerDes tuning parameters match the chip option, so the
* SerDes interface modes can be advertised
+ * @sds_reboot_nb: disables @sds_relatch before the devices are shut down
+ * @sds_relatch: re-latch edges and link health check (family D)
+ * @sds_relatch_count: next attempt of the re-latch episode, 0 once latched
+ * @sds_misc_target_val: SDS_MISC_CFG_MASK fields the re-latch work restores
+ * @sds_relatch_armed: pcs_config() set up 2500base-x; the re-latch work may run
+ * @sds_conduit_up: the conduit of the CPU port that carries the SerDes (port 6)
+ * is admin and oper up
*
* Private data for this driver.
*/
@@ -951,9 +990,17 @@ struct rtl8365mb {
const struct rtl8365mb_chip_info *chip_info;
struct rtl8365mb_cpu cpu;
struct mutex mib_lock;
+ struct mutex sds_cfg_lock;
+ struct mutex sds_lock;
struct rtl8365mb_port ports[RTL8365MB_MAX_NUM_PORTS];
struct phylink_pcs pcs;
bool sds_supported;
+ struct notifier_block sds_reboot_nb;
+ struct delayed_work sds_relatch;
+ unsigned int sds_relatch_count;
+ u32 sds_misc_target_val;
+ bool sds_relatch_armed;
+ bool sds_conduit_up;
};
#define pcs_to_rtl8365mb(_pcs) container_of((_pcs), struct rtl8365mb, pcs)
@@ -1357,43 +1404,53 @@ static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port,
static int rtl8365mb_sds_write(struct realtek_priv *priv, u8 index,
u16 addr, u16 data)
{
+ struct rtl8365mb *mb = priv->chip_data;
int ret;
+ mutex_lock(&mb->sds_lock);
+
ret = regmap_write(priv->map, RTL8365MB_SDS_INDACS_DATA_REG, data);
if (ret)
- return ret;
+ goto out_unlock;
ret = regmap_write(priv->map, RTL8365MB_SDS_INDACS_ADR_REG, addr);
if (ret)
- return ret;
+ goto out_unlock;
/* The SerDes indirect access engine completes the command within the
* register write transaction, so there is no need to wait or poll for
* completion before the next access, matching the vendor driver.
*/
- return regmap_write(priv->map, RTL8365MB_SDS_INDACS_CMD_REG,
- RTL8365MB_SDS_INDACS_CMD_RUN_MASK |
- RTL8365MB_SDS_INDACS_CMD_WR_MASK |
- FIELD_PREP(RTL8365MB_SDS_INDACS_CMD_INDEX_MASK,
- index));
+ ret = regmap_write(priv->map, RTL8365MB_SDS_INDACS_CMD_REG,
+ RTL8365MB_SDS_INDACS_CMD_RUN_MASK |
+ RTL8365MB_SDS_INDACS_CMD_WR_MASK |
+ FIELD_PREP(RTL8365MB_SDS_INDACS_CMD_INDEX_MASK,
+ index));
+
+out_unlock:
+ mutex_unlock(&mb->sds_lock);
+ return ret;
}
static int rtl8365mb_sds_read(struct realtek_priv *priv, u8 index,
u16 addr, u16 *data)
{
+ struct rtl8365mb *mb = priv->chip_data;
u32 val;
int ret;
+ mutex_lock(&mb->sds_lock);
+
ret = regmap_write(priv->map, RTL8365MB_SDS_INDACS_ADR_REG, addr);
if (ret)
- return ret;
+ goto out_unlock;
ret = regmap_write(priv->map, RTL8365MB_SDS_INDACS_CMD_REG,
RTL8365MB_SDS_INDACS_CMD_RUN_MASK |
FIELD_PREP(RTL8365MB_SDS_INDACS_CMD_INDEX_MASK,
index));
if (ret)
- return ret;
+ goto out_unlock;
/* Wait for the indirect read to complete: the engine clears the BUSY
* bit once the data register holds the result.
@@ -1403,15 +1460,19 @@ static int rtl8365mb_sds_read(struct realtek_priv *priv, u8 index,
!(val & RTL8365MB_SDS_INDACS_CMD_BUSY_MASK),
10, 1000);
if (ret)
- return ret;
+ goto out_unlock;
ret = regmap_read(priv->map, RTL8365MB_SDS_INDACS_DATA_REG, &val);
if (ret)
- return ret;
+ goto out_unlock;
*data = val;
- return 0;
+ ret = 0;
+
+out_unlock:
+ mutex_unlock(&mb->sds_lock);
+ return ret;
}
/* The vendor driver selects between two sets of SerDes tuning parameters based
@@ -1512,6 +1573,37 @@ static int rtl8365mb_sds_raise_rate_limits(struct realtek_priv *priv)
RTL8365MB_PORT6_EGRESSBW_CTRL1_MASK);
}
+static void rtl8365mb_sds_relatch_start(struct rtl8365mb *mb)
+{
+ WRITE_ONCE(mb->sds_relatch_count, 1);
+ schedule_delayed_work(&mb->sds_relatch, 0);
+}
+
+/* Put SDS_MISC back to the target mode. The lane stays parked (mode field
+ * DISABLE) until this succeeds, so retry a few times before giving up until
+ * the next run.
+ */
+static int rtl8365mb_sds_relatch_restore(struct rtl8365mb *mb)
+{
+ struct realtek_priv *priv = mb->priv;
+ int ret = 0;
+ int i;
+
+ for (i = 0; i < RTL8365MB_D_SDS_RESTORE_TRIES; i++) {
+ ret = regmap_update_bits(priv->map, RTL8365MB_SDS_MISC_REG,
+ RTL8365MB_D_SDS_MISC_CFG_MASK,
+ READ_ONCE(mb->sds_misc_target_val));
+ if (!ret)
+ return 0;
+ if (i < RTL8365MB_D_SDS_RESTORE_TRIES - 1)
+ usleep_range(1000, 2000);
+ }
+
+ dev_err_ratelimited(priv->dev, "failed to restore SDS_MISC: %pe\n",
+ ERR_PTR(ret));
+ return ret;
+}
+
static int rtl8365mb_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
phy_interface_t interface,
const unsigned long *advertising,
@@ -1533,6 +1625,17 @@ static int rtl8365mb_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
is_d = rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D;
+ guard(mutex)(&mb->sds_cfg_lock);
+
+ /* Cancel any in-flight re-latch edge before touching SDS_MISC: the
+ * work parks SDS_MISC and restores the target value after a sleep, so
+ * it could otherwise write a stale target over the new configuration.
+ */
+ if (is_d) {
+ WRITE_ONCE(mb->sds_relatch_armed, false);
+ cancel_delayed_work_sync(&mb->sds_relatch);
+ }
+
/* Select the appropriate tuning table and SDS mode */
if (interface == PHY_INTERFACE_MODE_2500BASEX) {
if (is_d) {
@@ -1622,7 +1725,9 @@ static int rtl8365mb_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
if (ret)
return ret;
- if (!is_d) {
+ if (is_d) {
+ WRITE_ONCE(mb->sds_misc_target_val, misc_val);
+ } else {
val = sds_mode << RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(id);
ret = regmap_update_bits(priv->map,
RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(id),
@@ -1670,8 +1775,192 @@ static int rtl8365mb_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
val &= ~RTL8365MB_SDS_NWAY_EN_MASK;
val |= RTL8365MB_SDS_NWAY_RESTART_MASK;
- return rtl8365mb_sds_write(priv, sds_index,
- RTL8365MB_SDS_REG_NWAY, val);
+ ret = rtl8365mb_sds_write(priv, sds_index,
+ RTL8365MB_SDS_REG_NWAY, val);
+ if (ret)
+ return ret;
+
+ /* The re-latch edge has only been observed with HSGMII, so the work is
+ * only armed for 2500base-x. It starts once the conduit is up.
+ */
+ if (is_d) {
+ WRITE_ONCE(mb->sds_relatch_armed,
+ interface == PHY_INTERFACE_MODE_2500BASEX);
+ /* With the conduit already up no conduit_state_change() will
+ * follow, so start the episode here.
+ */
+ if (READ_ONCE(mb->sds_relatch_armed) &&
+ READ_ONCE(mb->sds_conduit_up))
+ rtl8365mb_sds_relatch_start(mb);
+ }
+
+ return 0;
+}
+
+static void rtl8365mb_conduit_state_change(struct dsa_switch *ds,
+ const struct net_device *conduit,
+ bool operational)
+{
+ struct dsa_port *cpu_dp = conduit->dsa_ptr;
+ struct realtek_priv *priv = ds->priv;
+ struct rtl8365mb *mb = priv->chip_data;
+
+ if (rtl8365mb_get_family(priv) != RTL8365MB_FAMILY_D)
+ return;
+
+ /* The chip can have two CPU ports (SerDes on port 6, RGMII on
+ * port 7) and DSA reports every conduit. Only the one behind the
+ * SerDes matters here.
+ */
+ if (cpu_dp->index != RTL8365MB_SDS_EXT_INTERFACE_PORT)
+ return;
+
+ guard(mutex)(&mb->sds_cfg_lock);
+
+ WRITE_ONCE(mb->sds_conduit_up, operational);
+ cancel_delayed_work_sync(&mb->sds_relatch);
+ if (operational && READ_ONCE(mb->sds_relatch_armed))
+ rtl8365mb_sds_relatch_start(mb);
+}
+
+/* The family D receiver latches on a DISABLE -> mode edge in SDS_MISC
+ * rather than on the value, and only once the far-end MAC has brought up
+ * its half of the link. No local signal predicts that (bit 8 of the SDS
+ * link-status word does not change ahead of it), so the work cannot wait
+ * for it, only check afterwards whether an edge took. Nor does phylink
+ * call rtl8365mb_pcs_get_state() for a link without in-band signalling
+ * such as the fixed-link CPU trunk (mb->pcs.poll only arms phylink's own
+ * poll for in-band links), so this cannot rely on being polled at all.
+ * Instead, an episode starts when the conduit comes up (see
+ * rtl8365mb_conduit_state_change(), or pcs_config() if it is already up)
+ * and this work re-arms itself.
+ *
+ * An episode is capped at RTL8365MB_D_SDS_RELATCH_MAX_TRIES edges, spaced
+ * RTL8365MB_D_SDS_RELATCH_INTERVAL apart, so that a far end which never
+ * comes up costs a bounded burst of 20 ms parks. The run after the last
+ * edge only checks whether it took and reports failure; from then on one
+ * edge is driven per RTL8365MB_D_SDS_HEALTHCHECK_INTERVAL, so a far end
+ * that comes up late is recovered without a reconfiguration. Once the
+ * receiver has latched the work just polls the link at the same slow
+ * interval; finding it down then starts a new episode, e.g. after the far
+ * end reset its PLL without a reconfiguration.
+ *
+ * sds_relatch_count is the number of the next attempt of the episode: 0
+ * while latched, 1..MAX_TRIES in budget, MAX_TRIES + 1 for the run that
+ * only reports, and above that once out of budget.
+ */
+static void rtl8365mb_sds_relatch_work(struct work_struct *work)
+{
+ struct rtl8365mb *mb = container_of(to_delayed_work(work),
+ struct rtl8365mb, sds_relatch);
+ struct realtek_priv *priv = mb->priv;
+ u32 park = (READ_ONCE(mb->sds_misc_target_val) &
+ ~RTL8365MB_D_SDS_MISC_MODE_FIELD_MASK) |
+ RTL8365MB_D_PORT_SDS_MODE_DISABLE;
+ unsigned long delay = RTL8365MB_D_SDS_RELATCH_INTERVAL;
+ unsigned int attempts;
+ u16 status;
+ u32 misc;
+ int ret;
+
+ /* An earlier run may have failed to restore the target mode, which
+ * leaves the lane parked. The mode field in SDS_MISC says so: put it
+ * back before anything else.
+ */
+ ret = regmap_read(priv->map, RTL8365MB_SDS_MISC_REG, &misc);
+ if (ret) {
+ dev_err_ratelimited(priv->dev,
+ "failed to read SDS_MISC: %pe\n",
+ ERR_PTR(ret));
+ goto rearm;
+ }
+ if ((misc & RTL8365MB_D_SDS_MISC_MODE_FIELD_MASK) ==
+ RTL8365MB_D_PORT_SDS_MODE_DISABLE) {
+ rtl8365mb_sds_relatch_restore(mb);
+ goto rearm;
+ }
+
+ /* The condition that queued this work may already be stale by the
+ * time it runs (e.g. an earlier edge from a prior attempt just
+ * latched). Parking an already-live link would drop it for no
+ * reason.
+ */
+ ret = rtl8365mb_sds_read(priv, RTL8365MB_D_SDS_EXT0_INDEX,
+ RTL8365MB_SDS_REG_LINK_STATUS, &status);
+ if (ret) {
+ dev_err_ratelimited(priv->dev,
+ "failed to read SerDes link status: %pe\n",
+ ERR_PTR(ret));
+ goto rearm;
+ }
+ if (status & RTL8365MB_SDS_LINK_STATUS_LINK_MASK) {
+ /* Latched: end the episode, keep watching for a later loss. */
+ WRITE_ONCE(mb->sds_relatch_count, 0);
+ delay = RTL8365MB_D_SDS_HEALTHCHECK_INTERVAL;
+ goto rearm;
+ }
+
+ attempts = READ_ONCE(mb->sds_relatch_count);
+ if (!attempts) {
+ dev_warn(priv->dev,
+ "SerDes link lost outside a reconfiguration; re-latching\n");
+ attempts = 1;
+ } else if (attempts == RTL8365MB_D_SDS_RELATCH_MAX_TRIES + 1) {
+ /* This run only checked whether the last in-budget edge
+ * took. The first out-of-budget edge comes one healthcheck
+ * interval from now, not on this pass.
+ */
+ WRITE_ONCE(mb->sds_relatch_count, attempts + 1);
+ dev_warn(priv->dev,
+ "SerDes did not latch after %u re-latch attempts; still retrying every %d s\n",
+ RTL8365MB_D_SDS_RELATCH_MAX_TRIES,
+ RTL8365MB_D_SDS_HEALTHCHECK_INTERVAL / HZ);
+ delay = RTL8365MB_D_SDS_HEALTHCHECK_INTERVAL;
+ goto rearm;
+ }
+
+ if (attempts <= RTL8365MB_D_SDS_RELATCH_MAX_TRIES)
+ WRITE_ONCE(mb->sds_relatch_count, attempts + 1);
+ else
+ /* Past the fast-retry budget. The receiver latches only on a
+ * DISABLE -> mode edge and nothing re-runs pcs_config() for a
+ * link without in-band signalling, so keep driving one edge
+ * per interval.
+ */
+ delay = RTL8365MB_D_SDS_HEALTHCHECK_INTERVAL;
+
+ ret = regmap_update_bits(priv->map, RTL8365MB_SDS_MISC_REG,
+ RTL8365MB_D_SDS_MISC_CFG_MASK, park);
+ if (ret) {
+ dev_err_ratelimited(priv->dev,
+ "failed to park SDS_MISC: %pe\n",
+ ERR_PTR(ret));
+ goto rearm;
+ }
+
+ usleep_range(20000, 21000);
+
+ if (rtl8365mb_sds_relatch_restore(mb)) {
+ /* The SerDes is left parked: come back soon rather than
+ * at the (possibly 10 s) pace chosen above.
+ */
+ delay = RTL8365MB_D_SDS_RELATCH_INTERVAL;
+ goto rearm;
+ }
+
+ dev_dbg(priv->dev, "SerDes re-latch edge driven (attempt %u)\n",
+ attempts);
+
+ /* This edge may not have taken either; the next run checks. */
+rearm:
+ schedule_delayed_work(&mb->sds_relatch, delay);
+}
+
+static void rtl8365mb_sds_relatch_disable(void *data)
+{
+ struct rtl8365mb *mb = data;
+
+ disable_delayed_work_sync(&mb->sds_relatch);
}
static bool rtl8365mb_interface_is_serdes(phy_interface_t interface)
@@ -1825,11 +2114,25 @@ static void rtl8365mb_pcs_link_up(struct phylink_pcs *pcs,
}
}
+static void rtl8365mb_pcs_disable(struct phylink_pcs *pcs)
+{
+ struct rtl8365mb *mb = pcs_to_rtl8365mb(pcs);
+
+ if (rtl8365mb_get_family(mb->priv) != RTL8365MB_FAMILY_D)
+ return;
+
+ guard(mutex)(&mb->sds_cfg_lock);
+
+ WRITE_ONCE(mb->sds_relatch_armed, false);
+ cancel_delayed_work_sync(&mb->sds_relatch);
+}
+
static const struct phylink_pcs_ops rtl8365mb_pcs_ops = {
.pcs_inband_caps = rtl8365mb_pcs_inband_caps,
.pcs_config = rtl8365mb_pcs_config,
.pcs_get_state = rtl8365mb_pcs_get_state,
.pcs_link_up = rtl8365mb_pcs_link_up,
+ .pcs_disable = rtl8365mb_pcs_disable,
};
static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port,
@@ -3563,6 +3866,14 @@ out_error:
static void rtl8365mb_teardown(struct dsa_switch *ds)
{
struct realtek_priv *priv = ds->priv;
+ struct rtl8365mb *mb = priv->chip_data;
+
+ if (rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D) {
+ guard(mutex)(&mb->sds_cfg_lock);
+
+ WRITE_ONCE(mb->sds_relatch_armed, false);
+ cancel_delayed_work_sync(&mb->sds_relatch);
+ }
rtl8365mb_stats_teardown(priv);
rtl8365mb_irq_teardown(priv);
@@ -3595,6 +3906,23 @@ static int rtl8365mb_get_chip_id_and_ver(struct regmap *map, u32 *id, u32 *ver)
return 0;
}
+static int rtl8365mb_sds_reboot_notify(struct notifier_block *nb,
+ unsigned long action, void *data)
+{
+ struct rtl8365mb *mb = container_of(nb, struct rtl8365mb,
+ sds_reboot_nb);
+
+ /* Runs before device_shutdown() on reboot, halt, power off and kexec.
+ * disable_delayed_work_sync() waits for a running pass and keeps
+ * pcs_config() from queueing the work again, so the bus is not
+ * touched once it is being shut down. If the last restore failed the
+ * lane stays parked until the next pcs_config().
+ */
+ disable_delayed_work_sync(&mb->sds_relatch);
+
+ return NOTIFY_DONE;
+}
+
static int rtl8365mb_detect(struct realtek_priv *priv)
{
struct rtl8365mb *mb = priv->chip_data;
@@ -3630,6 +3958,34 @@ static int rtl8365mb_detect(struct realtek_priv *priv)
priv->num_ports = RTL8365MB_MAX_NUM_PORTS;
mb->priv = priv;
+
+ ret = devm_mutex_init(priv->dev, &mb->sds_lock);
+ if (ret)
+ return ret;
+
+ ret = devm_mutex_init(priv->dev, &mb->sds_cfg_lock);
+ if (ret)
+ return ret;
+
+ if (rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D) {
+ /* Registered after sds_lock, so on release the work is
+ * disabled before the mutex is destroyed.
+ */
+ INIT_DELAYED_WORK(&mb->sds_relatch,
+ rtl8365mb_sds_relatch_work);
+ ret = devm_add_action_or_reset(priv->dev,
+ rtl8365mb_sds_relatch_disable,
+ mb);
+ if (ret)
+ return ret;
+
+ mb->sds_reboot_nb.notifier_call = rtl8365mb_sds_reboot_notify;
+ ret = devm_register_reboot_notifier(priv->dev,
+ &mb->sds_reboot_nb);
+ if (ret)
+ return ret;
+ }
+
mb->cpu.trap_port = RTL8365MB_MAX_NUM_PORTS;
mb->cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL;
mb->cpu.position = RTL8365MB_CPU_POS_AFTER_SA;
@@ -3714,6 +4070,7 @@ static const struct dsa_switch_ops rtl8365mb_switch_ops = {
.port_vlan_add = rtl8365mb_port_vlan_add,
.port_vlan_del = rtl8365mb_port_vlan_del,
.port_vlan_filtering = rtl8365mb_port_vlan_filtering,
+ .conduit_state_change = rtl8365mb_conduit_state_change,
.get_strings = rtl8365mb_get_strings,
.get_ethtool_stats = rtl8365mb_get_ethtool_stats,
.get_sset_count = rtl8365mb_get_sset_count,
--
2.53.0
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH net-next v7 09/10] net: dsa: realtek: rtl8365mb: make L2/LUT access work on family D
2026-11-02 14:34 ` [PATCH net-next v7 0/10] net: dsa: realtek: rtl8365mb: add support for RTL8367S-VB Mieczyslaw Nalewaj
` (7 preceding siblings ...)
2026-11-02 14:43 ` [PATCH net-next v7 08/10] net: dsa: realtek: rtl8365mb: re-latch the family D SerDes Mieczyslaw Nalewaj
@ 2026-11-02 14:44 ` Mieczyslaw Nalewaj
2026-11-02 14:45 ` [PATCH net-next v7 10/10] net: dsa: realtek: rtl8365mb: add support for RTL8367S-VB Mieczyslaw Nalewaj
9 siblings, 0 replies; 11+ messages in thread
From: Mieczyslaw Nalewaj @ 2026-11-02 14:44 UTC (permalink / raw)
To: linusw, andrew, olteanv, kuba, davem, edumazet, pabeni, linux,
luizluca, maxime.chevallier, netdev, linux-kernel
The L2 lookup table on family D switches (e.g. RTL8367S-VB) differs
from family C in ways that make the current FDB/MDB code misbehave:
- An L2 entry is 5 words instead of 6, with a different field layout
in words 3 and 4 (port, age, static and multicast member bits).
- There is no EFID and no per-bridge FDB isolation. The register at
0x0A32, used as the per-port EFID register on family C, is the LUT
aging timer on family D, so writing an EFID there corrupts it.
- In the table access interface, the SPA field is 3 bits wide and the
address register is 12 bits wide, with no address extension bit.
- Only ports 0..7 are present in the LUT and there is no
FLUSH_PORT_EXT register.
Teach the table and L2 code about these differences, selecting the
layout at runtime with rtl8365mb_get_family(). Family C behaviour is
unchanged.
Specifically:
- rtl8365mb_table: use the family D port mask and address width, and
read the hit address from status bits [11:0].
- rtl8365mb_l2: add family D unicast/multicast entry (de)serialisers
behind *_any() wrappers, pass the proper entry size to the table
layer, reject ports above 7, report SVL (FID) entries with VID 0.
Use age 6 for static unicast entries as the vendor code does, and
look an entry up before deleting it so that a missing entry is not
allocated by the delete.
- rtl8365mb_main: make port_set_efid() a no-op on family D, add a LUT
init step that clears IPMC_HASH and BCAM_DISABLE and programs the
aging timer, and do not advertise fdb_isolation or
max_num_bridges. Traffic between bridges is then isolated by the
port isolation masks only.
Register layouts were taken from the family D register description;
the code itself is an independent implementation.
No chip uses family D before the last patch of the series, so this code
is unreachable until then.
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
---
drivers/net/dsa/realtek/rtl8365mb_l2.c | 216 ++++++++++++++++++++--
drivers/net/dsa/realtek/rtl8365mb_main.c | 46 ++++-
drivers/net/dsa/realtek/rtl8365mb_table.c | 46 ++++-
3 files changed, 276 insertions(+), 32 deletions(-)
diff --git a/drivers/net/dsa/realtek/rtl8365mb_l2.c b/drivers/net/dsa/realtek/rtl8365mb_l2.c
index 0494d8a..a7613e2 100644
--- a/drivers/net/dsa/realtek/rtl8365mb_l2.c
+++ b/drivers/net/dsa/realtek/rtl8365mb_l2.c
@@ -8,9 +8,12 @@
#include "rtl8365mb_l2.h"
#include "rtl8365mb_table.h"
+#include "rtl8365mb.h"
#include <linux/regmap.h>
#define RTL8365MB_L2_ENTRY_SIZE 6
+#define RTL8365MB_D_L2_ENTRY_SIZE 5
+#define RTL8365MB_D_L2_MAX_PORT 7
#define RTL8365MB_L2_UC_D0_MAC5_MSK GENMASK(7, 0)
#define RTL8365MB_L2_UC_D0_MAC4_MSK GENMASK(15, 8)
@@ -58,6 +61,21 @@
#define RTL8365MB_L2_MC_D5_MBR_HI2_MSK GENMASK(7, 7)
#define RTL8365MB_L2_MC_MBR_HI2_MSK GENMASK(10, 10)
+/* Family D unicast (auto-learn / static) entry */
+#define RTL8365MB_D_L2_UC_D3_VID_MSK GENMASK(11, 0)
+#define RTL8365MB_D_L2_UC_D3_IVL_MSK BIT(13)
+#define RTL8365MB_D_L2_UC_D3_PORT_LO_MSK GENMASK(15, 14)
+#define RTL8365MB_D_L2_UC_D4_PORT_HI_MSK BIT(0)
+#define RTL8365MB_D_L2_UC_D4_AGE_MSK GENMASK(3, 1)
+#define RTL8365MB_D_L2_UC_D4_STATIC_MSK BIT(6)
+
+/* Family D multicast entry */
+#define RTL8365MB_D_L2_MC_D3_VID_MSK GENMASK(11, 0)
+#define RTL8365MB_D_L2_MC_D3_IVL_MSK BIT(13)
+#define RTL8365MB_D_L2_MC_D3_MBR_LO_MSK GENMASK(15, 14)
+#define RTL8365MB_D_L2_MC_D4_MBR_HI_MSK GENMASK(5, 0)
+#define RTL8365MB_D_L2_MC_D4_STATIC_MSK BIT(6)
+
/* Port flush command registers - writing a 1 to the port's MASK bit will
* initiate the flush procedure. Completion is signalled when the corresponding
* BUSY bit is 0.
@@ -258,6 +276,130 @@ static void rtl8365mb_l2_mc_to_data(const struct rtl8365mb_l2_mc *mc, u16 *data)
data[5] |= FIELD_PREP(RTL8365MB_L2_MC_D5_MBR_HI2_MSK, val);
}
+static bool rtl8365mb_l2_is_d(struct realtek_priv *priv)
+{
+ return rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D;
+}
+
+static size_t rtl8365mb_l2_entry_size(struct realtek_priv *priv)
+{
+ return rtl8365mb_l2_is_d(priv) ? RTL8365MB_D_L2_ENTRY_SIZE :
+ RTL8365MB_L2_ENTRY_SIZE;
+}
+
+static void rtl8365mb_l2_mac_to_data(const u8 *m, u16 *data)
+{
+ data[0] = (m[4] << 8) | m[5];
+ data[1] = (m[2] << 8) | m[3];
+ data[2] = (m[0] << 8) | m[1];
+}
+
+static void rtl8365mb_l2_data_to_mac(const u16 *data, u8 *m)
+{
+ m[5] = data[0] & 0xff;
+ m[4] = data[0] >> 8;
+ m[3] = data[1] & 0xff;
+ m[2] = data[1] >> 8;
+ m[1] = data[2] & 0xff;
+ m[0] = data[2] >> 8;
+}
+
+static void rtl8365mb_d_l2_data_to_uc(const u16 *data,
+ struct rtl8365mb_l2_uc *uc)
+{
+ rtl8365mb_l2_data_to_mac(data, uc->key.mac_addr);
+ uc->key.vid = FIELD_GET(RTL8365MB_D_L2_UC_D3_VID_MSK, data[3]);
+ uc->key.ivl = FIELD_GET(RTL8365MB_D_L2_UC_D3_IVL_MSK, data[3]);
+ uc->key.fid = 0;
+ uc->key.efid = 0;
+ uc->port = FIELD_GET(RTL8365MB_D_L2_UC_D3_PORT_LO_MSK, data[3]) |
+ (FIELD_GET(RTL8365MB_D_L2_UC_D4_PORT_HI_MSK, data[4]) << 2);
+ uc->age = FIELD_GET(RTL8365MB_D_L2_UC_D4_AGE_MSK, data[4]);
+ uc->is_static = FIELD_GET(RTL8365MB_D_L2_UC_D4_STATIC_MSK, data[4]);
+}
+
+static void rtl8365mb_d_l2_uc_to_data(const struct rtl8365mb_l2_uc *uc,
+ u16 *data)
+{
+ memset(data, 0, RTL8365MB_L2_ENTRY_SIZE * 2);
+ rtl8365mb_l2_mac_to_data(uc->key.mac_addr, data);
+ data[3] = FIELD_PREP(RTL8365MB_D_L2_UC_D3_VID_MSK, uc->key.vid) |
+ FIELD_PREP(RTL8365MB_D_L2_UC_D3_IVL_MSK, uc->key.ivl) |
+ FIELD_PREP(RTL8365MB_D_L2_UC_D3_PORT_LO_MSK, uc->port & 0x3);
+ data[4] = FIELD_PREP(RTL8365MB_D_L2_UC_D4_PORT_HI_MSK,
+ (uc->port >> 2) & 0x1) |
+ FIELD_PREP(RTL8365MB_D_L2_UC_D4_AGE_MSK, uc->age) |
+ FIELD_PREP(RTL8365MB_D_L2_UC_D4_STATIC_MSK, uc->is_static);
+}
+
+static void rtl8365mb_d_l2_data_to_mc(const u16 *data,
+ struct rtl8365mb_l2_mc *mc)
+{
+ rtl8365mb_l2_data_to_mac(data, mc->key.mac_addr);
+ mc->key.vid = FIELD_GET(RTL8365MB_D_L2_MC_D3_VID_MSK, data[3]);
+ mc->key.ivl = FIELD_GET(RTL8365MB_D_L2_MC_D3_IVL_MSK, data[3]);
+ mc->member = FIELD_GET(RTL8365MB_D_L2_MC_D3_MBR_LO_MSK, data[3]) |
+ (FIELD_GET(RTL8365MB_D_L2_MC_D4_MBR_HI_MSK, data[4]) << 2);
+ mc->is_static = FIELD_GET(RTL8365MB_D_L2_MC_D4_STATIC_MSK, data[4]);
+ mc->igmpidx = 0;
+ mc->priority = 0;
+ mc->fwd_pri = 0;
+ mc->igmp_asic = 0;
+}
+
+static void rtl8365mb_d_l2_mc_to_data(const struct rtl8365mb_l2_mc *mc,
+ u16 *data)
+{
+ memset(data, 0, RTL8365MB_L2_ENTRY_SIZE * 2);
+ rtl8365mb_l2_mac_to_data(mc->key.mac_addr, data);
+ data[3] = FIELD_PREP(RTL8365MB_D_L2_MC_D3_VID_MSK, mc->key.vid) |
+ FIELD_PREP(RTL8365MB_D_L2_MC_D3_IVL_MSK, mc->key.ivl) |
+ FIELD_PREP(RTL8365MB_D_L2_MC_D3_MBR_LO_MSK, mc->member & 0x3);
+ data[4] = FIELD_PREP(RTL8365MB_D_L2_MC_D4_MBR_HI_MSK,
+ (mc->member >> 2) & 0x3f) |
+ FIELD_PREP(RTL8365MB_D_L2_MC_D4_STATIC_MSK, mc->is_static);
+}
+
+static void rtl8365mb_l2_data_to_uc_any(struct realtek_priv *priv,
+ const u16 *data,
+ struct rtl8365mb_l2_uc *uc)
+{
+ if (rtl8365mb_l2_is_d(priv))
+ rtl8365mb_d_l2_data_to_uc(data, uc);
+ else
+ rtl8365mb_l2_data_to_uc(data, uc);
+}
+
+static void rtl8365mb_l2_uc_to_data_any(struct realtek_priv *priv,
+ const struct rtl8365mb_l2_uc *uc,
+ u16 *data)
+{
+ if (rtl8365mb_l2_is_d(priv))
+ rtl8365mb_d_l2_uc_to_data(uc, data);
+ else
+ rtl8365mb_l2_uc_to_data(uc, data);
+}
+
+static void rtl8365mb_l2_data_to_mc_any(struct realtek_priv *priv,
+ const u16 *data,
+ struct rtl8365mb_l2_mc *mc)
+{
+ if (rtl8365mb_l2_is_d(priv))
+ rtl8365mb_d_l2_data_to_mc(data, mc);
+ else
+ rtl8365mb_l2_data_to_mc(data, mc);
+}
+
+static void rtl8365mb_l2_mc_to_data_any(struct realtek_priv *priv,
+ const struct rtl8365mb_l2_mc *mc,
+ u16 *data)
+{
+ if (rtl8365mb_l2_is_d(priv))
+ rtl8365mb_d_l2_mc_to_data(mc, data);
+ else
+ rtl8365mb_l2_mc_to_data(mc, data);
+}
+
/*
* rtl8365mb_l2_get_next_uc() - get the next Unicast L2 entry
* @priv: realtek_priv pointer
@@ -286,17 +428,23 @@ int rtl8365mb_l2_get_next_uc(struct realtek_priv *priv, u16 *addr, int port,
struct rtl8365mb_l2_uc uc;
int ret;
+ if (rtl8365mb_l2_is_d(priv) && port > RTL8365MB_D_L2_MAX_PORT)
+ return -EINVAL;
+
ret = rtl8365mb_table_query(priv, RTL8365MB_TABLE_L2,
RTL8365MB_TABLE_OP_READ, addr,
RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_UC_PORT,
- port, data, RTL8365MB_L2_ENTRY_SIZE);
+ port, data, rtl8365mb_l2_entry_size(priv));
if (ret)
return ret;
- rtl8365mb_l2_data_to_uc(data, &uc);
+ rtl8365mb_l2_data_to_uc_any(priv, data, &uc);
ether_addr_copy(entry->mac_addr, uc.key.mac_addr);
- entry->vid = uc.key.vid;
+ /* D has one shared VID/FID field; report SVL (FID) entries with
+ * vid 0 as they have no VLAN to be shown under
+ */
+ entry->vid = (rtl8365mb_l2_is_d(priv) && !uc.key.ivl) ? 0 : uc.key.vid;
entry->is_static = uc.is_static;
return 0;
@@ -311,6 +459,9 @@ int rtl8365mb_l2_add_uc(struct realtek_priv *priv, int port,
u16 addr;
int ret;
+ if (rtl8365mb_l2_is_d(priv) && port > RTL8365MB_D_L2_MAX_PORT)
+ return -EINVAL;
+
memcpy(uc.key.mac_addr, mac_addr, ETH_ALEN);
uc.key.efid = efid;
uc.key.fid = 0;
@@ -324,15 +475,18 @@ int rtl8365mb_l2_add_uc(struct realtek_priv *priv, int port,
* OS's back. As a trade-off, these will show up as permanent to users.
*/
uc.is_static = true;
- /* age greater than 0 adds/updates entries */
- uc.age = 1;
- rtl8365mb_l2_uc_to_data(&uc, data);
+ /* age greater than 0 adds/updates entries. D has no EFID, so efid is
+ * not serialised (bridges are isolated by the port isolation masks only).
+ * Vendor code writes age 6 for D.
+ */
+ uc.age = rtl8365mb_l2_is_d(priv) ? 6 : 1;
+ rtl8365mb_l2_uc_to_data_any(priv, &uc, data);
/* add the new entry or update an existing one */
ret = rtl8365mb_table_query(priv, RTL8365MB_TABLE_L2,
RTL8365MB_TABLE_OP_WRITE, &addr,
0, 0,
- data, RTL8365MB_L2_ENTRY_SIZE);
+ data, rtl8365mb_l2_entry_size(priv));
/* Assume the missing new entry as the table is full */
if (ret == -ENOENT)
@@ -358,7 +512,25 @@ int rtl8365mb_l2_del_uc(struct realtek_priv *priv, int port,
uc.key.vid = vid;
/* age 0 deletes the entry */
uc.age = 0;
- rtl8365mb_l2_uc_to_data(&uc, data);
+ rtl8365mb_l2_uc_to_data_any(priv, &uc, data);
+
+ if (rtl8365mb_l2_is_d(priv)) {
+ /* Do not blind-write: look the entry up first (as the vendor
+ * code does) so a missing entry is not (re)allocated.
+ */
+ ret = rtl8365mb_table_query(priv, RTL8365MB_TABLE_L2,
+ RTL8365MB_TABLE_OP_READ, &addr,
+ RTL8365MB_TABLE_L2_METHOD_MAC, 0,
+ data,
+ rtl8365mb_l2_entry_size(priv));
+ if (ret == -ENOENT)
+ return 0;
+ if (ret)
+ return ret;
+
+ /* rebuild the write payload: the read overwrote data[] */
+ rtl8365mb_l2_uc_to_data_any(priv, &uc, data);
+ }
/* it looks like the switch will always add/update the entry,
* even when age is 0 or uc.key did not match an existing entry,
@@ -368,7 +540,7 @@ int rtl8365mb_l2_del_uc(struct realtek_priv *priv, int port,
ret = rtl8365mb_table_query(priv, RTL8365MB_TABLE_L2,
RTL8365MB_TABLE_OP_WRITE, &addr,
0, 0,
- data, RTL8365MB_L2_ENTRY_SIZE);
+ data, rtl8365mb_l2_entry_size(priv));
if (ret == -ENOENT) {
dev_dbg(priv->dev, "%s: %pM vid=%d efid=%d missing\n",
@@ -388,6 +560,9 @@ int rtl8365mb_l2_flush(struct realtek_priv *priv, int port, u16 vid)
u32 val, mask;
int ret;
+ if (rtl8365mb_l2_is_d(priv) && port > RTL8365MB_D_L2_MAX_PORT)
+ return -EINVAL;
+
mutex_lock(&priv->map_lock);
/* Configure flushing mode; only flush dynamic entries */
@@ -455,6 +630,9 @@ int rtl8365mb_l2_add_mc(struct realtek_priv *priv, int port,
u16 addr;
int ret;
+ if (rtl8365mb_l2_is_d(priv) && port > RTL8365MB_D_L2_MAX_PORT)
+ return -EINVAL;
+
memcpy(mc.key.mac_addr, mac_addr, ETH_ALEN);
mc.key.vid = vid;
mc.key.ivl = true;
@@ -463,16 +641,16 @@ int rtl8365mb_l2_add_mc(struct realtek_priv *priv, int port,
*/
mc.member |= BIT(port);
mc.is_static = 1;
- rtl8365mb_l2_mc_to_data(&mc, data);
+ rtl8365mb_l2_mc_to_data_any(priv, &mc, data);
/* First look for an existing entry (to get existing port members) */
ret = rtl8365mb_table_query(priv, RTL8365MB_TABLE_L2,
RTL8365MB_TABLE_OP_READ, &addr,
RTL8365MB_TABLE_L2_METHOD_MAC, 0,
- data, RTL8365MB_L2_ENTRY_SIZE);
+ data, rtl8365mb_l2_entry_size(priv));
if (!ret) {
/* There is already an entry... */
- rtl8365mb_l2_data_to_mc(data, &mc);
+ rtl8365mb_l2_data_to_mc_any(priv, data, &mc);
dev_dbg(priv->dev,
"%s: found %pM addr=%d member=0x%x igmpidx=0x%x %s\n",
__func__, mac_addr, addr, mc.member, mc.igmpidx,
@@ -487,7 +665,7 @@ int rtl8365mb_l2_add_mc(struct realtek_priv *priv, int port,
mc.is_static = 1;
}
- rtl8365mb_l2_mc_to_data(&mc, data);
+ rtl8365mb_l2_mc_to_data_any(priv, &mc, data);
} else if (ret == -ENOENT) {
/* New entry, no need to update data again as it already
* includes the member.
@@ -508,7 +686,7 @@ int rtl8365mb_l2_add_mc(struct realtek_priv *priv, int port,
ret = rtl8365mb_table_query(priv, RTL8365MB_TABLE_L2,
RTL8365MB_TABLE_OP_WRITE, &addr,
0, 0,
- data, RTL8365MB_L2_ENTRY_SIZE);
+ data, rtl8365mb_l2_entry_size(priv));
/* Assume the missing new entry as the table is full */
if (ret == -ENOENT)
@@ -529,13 +707,13 @@ int rtl8365mb_l2_del_mc(struct realtek_priv *priv, int port,
memcpy(mc.key.mac_addr, mac_addr, ETH_ALEN);
mc.key.vid = vid;
mc.key.ivl = true;
- rtl8365mb_l2_mc_to_data(&mc, data);
+ rtl8365mb_l2_mc_to_data_any(priv, &mc, data);
/* First look for an existing entry (to get existing port members) */
ret = rtl8365mb_table_query(priv, RTL8365MB_TABLE_L2,
RTL8365MB_TABLE_OP_READ, &addr,
RTL8365MB_TABLE_L2_METHOD_MAC, 0,
- data, RTL8365MB_L2_ENTRY_SIZE);
+ data, rtl8365mb_l2_entry_size(priv));
if (ret == -ENOENT) {
dev_dbg(priv->dev, "%s: %pM vid=%d missing\n",
__func__, mac_addr, vid);
@@ -547,7 +725,7 @@ int rtl8365mb_l2_del_mc(struct realtek_priv *priv, int port,
/* Return on any other error */
return ret;
- rtl8365mb_l2_data_to_mc(data, &mc);
+ rtl8365mb_l2_data_to_mc_any(priv, data, &mc);
dev_dbg(priv->dev,
"%s: found %pM addr=%d member=0x%x igmpidx=0x%x %s\n",
__func__, mac_addr, addr, mc.member, mc.igmpidx,
@@ -565,12 +743,12 @@ int rtl8365mb_l2_del_mc(struct realtek_priv *priv, int port,
mc.fwd_pri = 0;
mc.igmp_asic = 0;
}
- rtl8365mb_l2_mc_to_data(&mc, data);
+ rtl8365mb_l2_mc_to_data_any(priv, &mc, data);
/* update the existing entry. */
ret = rtl8365mb_table_query(priv, RTL8365MB_TABLE_L2,
RTL8365MB_TABLE_OP_WRITE, &addr,
0, 0,
- data, RTL8365MB_L2_ENTRY_SIZE);
+ data, rtl8365mb_l2_entry_size(priv));
return ret;
}
diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/realtek/rtl8365mb_main.c
index 4937ffc..1c5f139 100644
--- a/drivers/net/dsa/realtek/rtl8365mb_main.c
+++ b/drivers/net/dsa/realtek/rtl8365mb_main.c
@@ -460,6 +460,14 @@
#define RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(_physport) \
(RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE + (_physport))
+/* Family D LUT configuration */
+#define RTL8365MB_D_LUT_CFG_REG 0x0A30
+#define RTL8365MB_D_LUT_CFG_BCAM_DISABLE_MASK BIT(6)
+#define RTL8365MB_D_LUT_CFG_IPMC_HASH_MASK BIT(4)
+/* On family C this address is the per-port EFID register! */
+#define RTL8365MB_D_LUT_CFG2_REG 0x0A32
+#define RTL8365MB_D_LUT_AGING_DEFAULT 3000
+
/* Port isolation (forwarding mask) registers */
#define RTL8365MB_PORT_ISOLATION_REG_BASE 0x08A2
#define RTL8365MB_PORT_ISOLATION_REG(_physport) \
@@ -2879,6 +2887,10 @@ static int rtl8365mb_port_pre_bridge_flags(struct dsa_switch *ds, int port,
static int rtl8365mb_port_set_efid(struct realtek_priv *priv, int port,
u32 efid)
{
+ /* Family D has no EFID; see RTL8365MB_D_LUT_CFG2_REG. */
+ if (rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D)
+ return 0;
+
return regmap_update_bits(priv->map, RTL8365MB_PORT_EFID_REG(port),
RTL8365MB_PORT_EFID_MASK(port),
efid << RTL8365MB_PORT_EFID_OFFSET(port));
@@ -3615,6 +3627,23 @@ static int rtl8365mb_change_tag_protocol(struct dsa_switch *ds,
return rtl8365mb_cpu_config(priv);
}
+static int rtl8365mb_d_lut_init(struct realtek_priv *priv)
+{
+ int ret;
+
+ /* After the jam table: lookup multicast by MAC (not DIP) and keep
+ * the CAM enabled.
+ */
+ ret = regmap_update_bits(priv->map, RTL8365MB_D_LUT_CFG_REG,
+ RTL8365MB_D_LUT_CFG_IPMC_HASH_MASK |
+ RTL8365MB_D_LUT_CFG_BCAM_DISABLE_MASK, 0);
+ if (ret)
+ return ret;
+
+ return regmap_write(priv->map, RTL8365MB_D_LUT_CFG2_REG,
+ RTL8365MB_D_LUT_AGING_DEFAULT);
+}
+
static int rtl8365mb_switch_init(struct realtek_priv *priv)
{
struct rtl8365mb *mb = priv->chip_data;
@@ -3704,6 +3733,15 @@ static int rtl8365mb_setup(struct dsa_switch *ds)
goto out_error;
}
+ if (rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D) {
+ ret = rtl8365mb_d_lut_init(priv);
+ if (ret) {
+ dev_err(priv->dev, "failed to init LUT: %pe\n",
+ ERR_PTR(ret));
+ goto out_error;
+ }
+ }
+
if (mb->sds_supported) {
ret = rtl8365mb_sds_raise_rate_limits(priv);
if (ret) {
@@ -3829,9 +3867,11 @@ static int rtl8365mb_setup(struct dsa_switch *ds)
goto out_teardown_irq;
ds->assisted_learning_on_cpu_port = true;
- ds->fdb_isolation = true;
- /* The EFID is 3 bits, but EFID 0 is reserved for standalone ports */
- ds->max_num_bridges = FIELD_MAX(RTL8365MB_EFID_MASK);
+ if (rtl8365mb_get_family(priv) != RTL8365MB_FAMILY_D) {
+ ds->fdb_isolation = true;
+ /* The EFID is 3 bits, but EFID 0 is reserved for standalone */
+ ds->max_num_bridges = FIELD_MAX(RTL8365MB_EFID_MASK);
+ }
ds->configure_vlan_while_not_filtering = true;
diff --git a/drivers/net/dsa/realtek/rtl8365mb_table.c b/drivers/net/dsa/realtek/rtl8365mb_table.c
index f3c8749..74a6aa7 100644
--- a/drivers/net/dsa/realtek/rtl8365mb_table.c
+++ b/drivers/net/dsa/realtek/rtl8365mb_table.c
@@ -5,6 +5,7 @@
*/
#include "rtl8365mb_table.h"
+#include "rtl8365mb.h"
#include <linux/regmap.h>
/* Table access control register */
@@ -16,10 +17,13 @@
/* Should be one of rtl8365mb_table_l2_method enum members */
#define RTL8365MB_TABLE_CTRL_METHOD_MASK GENMASK(6, 4)
#define RTL8365MB_TABLE_CTRL_PORT_MASK GENMASK(11, 8)
+/* Family D: SPA is 3 bits */
+#define RTL8365MB_D_TABLE_CTRL_PORT_MASK GENMASK(10, 8)
/* Table access address register */
#define RTL8365MB_TABLE_ACCESS_ADDR_REG 0x0501
#define RTL8365MB_TABLE_ADDR_MASK GENMASK(12, 0)
+#define RTL8365MB_D_TABLE_ADDR_MASK GENMASK(11, 0)
/* Table status register */
#define RTL8365MB_TABLE_STATUS_REG 0x0502
@@ -29,6 +33,8 @@
#define RTL8365MB_TABLE_STATUS_HIT_STATUS_MASK GENMASK(12, 12)
#define RTL8365MB_TABLE_STATUS_BUSY_FLAG_MASK GENMASK(13, 13)
#define RTL8365MB_TABLE_STATUS_ADDRESS_EXT_MASK GENMASK(14, 14)
+/* Family D: the address is bits [11:0], there is no EXT bit */
+#define RTL8365MB_D_TABLE_STATUS_ADDRESS_MASK GENMASK(11, 0)
/* Table read/write registers */
#define RTL8365MB_TABLE_WRITE_BASE 0x0510
@@ -59,6 +65,7 @@ int rtl8365mb_table_query(struct realtek_priv *priv,
{
bool addr_as_input = true;
bool write_data = false;
+ bool is_d = rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D;
int ret = 0;
u32 cmd;
u32 val;
@@ -91,7 +98,15 @@ int rtl8365mb_table_query(struct realtek_priv *priv,
case RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_MC:
break;
case RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_UC_PORT:
- cmd |= FIELD_PREP(RTL8365MB_TABLE_CTRL_PORT_MASK, port);
+ if (is_d) {
+ if (port > 7)
+ return -EINVAL;
+ cmd |= FIELD_PREP(RTL8365MB_D_TABLE_CTRL_PORT_MASK,
+ port);
+ } else {
+ cmd |= FIELD_PREP(RTL8365MB_TABLE_CTRL_PORT_MASK,
+ port);
+ }
break;
default:
return -EINVAL;
@@ -146,8 +161,9 @@ int rtl8365mb_table_query(struct realtek_priv *priv,
if (addr_as_input) {
ret = regmap_write(priv->map_nolock,
RTL8365MB_TABLE_ACCESS_ADDR_REG,
- FIELD_PREP(RTL8365MB_TABLE_ADDR_MASK,
- *addr));
+ is_d ?
+ FIELD_PREP(RTL8365MB_D_TABLE_ADDR_MASK, *addr) :
+ FIELD_PREP(RTL8365MB_TABLE_ADDR_MASK, *addr));
if (ret)
goto out;
}
@@ -177,13 +193,23 @@ int rtl8365mb_table_query(struct realtek_priv *priv,
}
/* If so, extract the address */
- *addr = 0;
- *addr |= FIELD_GET(RTL8365MB_TABLE_STATUS_ADDRESS_MASK, val);
- *addr |= FIELD_GET(RTL8365MB_TABLE_STATUS_ADDRESS_EXT_MASK, val)
- << 11;
- /* only set if it is a L3 address */
- *addr |= FIELD_GET(RTL8365MB_TABLE_STATUS_ADDR_TYPE_MASK, val)
- << 12;
+ if (is_d) {
+ /* Bit 11 is "TYPE" in the register map, but the entry
+ * index (2048 hash + 64 CAM) needs 12 bits; the vendor
+ * code reads [11:0] as well.
+ */
+ *addr = FIELD_GET(RTL8365MB_D_TABLE_STATUS_ADDRESS_MASK,
+ val);
+ } else {
+ *addr = 0;
+ *addr |= FIELD_GET(RTL8365MB_TABLE_STATUS_ADDRESS_MASK,
+ val);
+ *addr |= FIELD_GET(RTL8365MB_TABLE_STATUS_ADDRESS_EXT_MASK,
+ val) << 11;
+ /* only set if it is a L3 address */
+ *addr |= FIELD_GET(RTL8365MB_TABLE_STATUS_ADDR_TYPE_MASK,
+ val) << 12;
+ }
}
/* Finally, get the table entry if we were reading */
--
2.53.0
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH net-next v7 10/10] net: dsa: realtek: rtl8365mb: add support for RTL8367S-VB
2026-11-02 14:34 ` [PATCH net-next v7 0/10] net: dsa: realtek: rtl8365mb: add support for RTL8367S-VB Mieczyslaw Nalewaj
` (8 preceding siblings ...)
2026-11-02 14:44 ` [PATCH net-next v7 09/10] net: dsa: realtek: rtl8365mb: make L2/LUT access work on family D Mieczyslaw Nalewaj
@ 2026-11-02 14:45 ` Mieczyslaw Nalewaj
9 siblings, 0 replies; 11+ messages in thread
From: Mieczyslaw Nalewaj @ 2026-11-02 14:45 UTC (permalink / raw)
To: linusw, andrew, olteanv, kuba, davem, edumazet, pabeni, linux,
luizluca, maxime.chevallier, netdev, linux-kernel
Add the RTL8367S-VB (chip ID 0x6642, version 0x0010) to the chip table.
It is the first chip of family D, whose handling was added in the
preceding patches, so this is the patch that makes it reachable.
The SGMII/HSGMII SerDes of this chip sits on port 6 and the
MII/TMII/RMII/RGMII interface on port 7, as on family C, but the external
interface indices are one lower (EXT0 and EXT1 instead of EXT1 and EXT2).
The chip reuses the existing initialization jam table.
The chip has 8 ports, not 11. Cap priv->num_ports at
RTL8365MB_D_MAX_NUM_PORTS for family D. This is a functional change: it
sets ds->num_ports, the IRQ domain size and the bound of every loop over
priv->num_ports.
The L2 learning limit is the same as on family C (2112 entries), as
given by the Realtek rtl8367 common API (rtl8367_common V1.4.2), so
RTL8365MB_LEARN_LIMIT_MAX needs no per-family handling; only its
comment is updated.
Tested on a TP-Link Archer AX55 v1 (RTL8367S-VB, CPU port over HSGMII
to an IPQ5018) with bridge VLAN filtering and per-port PVIDs. SGMII has
also been seen working, but I no longer have the exact link partner and
speed it was tested with, so treat it as lightly tested. RGMII mode has
not yet been tested.
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
---
drivers/net/dsa/realtek/Kconfig | 3 ++-
drivers/net/dsa/realtek/rtl8365mb_main.c | 32 +++++++++++++++++++++---
2 files changed, 30 insertions(+), 5 deletions(-)
diff --git a/drivers/net/dsa/realtek/Kconfig b/drivers/net/dsa/realtek/Kconfig
index d6eb671..98b1727 100644
--- a/drivers/net/dsa/realtek/Kconfig
+++ b/drivers/net/dsa/realtek/Kconfig
@@ -34,7 +34,8 @@ config NET_DSA_REALTEK_RTL8365MB
depends on NET_DSA_REALTEK_SMI || NET_DSA_REALTEK_MDIO
select NET_DSA_TAG_RTL8_4
help
- Select to enable support for Realtek RTL8365MB-VC and RTL8367S.
+ Select to enable support for Realtek RTL8365MB-VC, RTL8367S and
+ RTL8367S-VB.
config NET_DSA_REALTEK_RTL8366RB
tristate "Realtek RTL8366RB switch driver"
diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/realtek/rtl8365mb_main.c
index 1c5f139..415468e 100644
--- a/drivers/net/dsa/realtek/rtl8365mb_main.c
+++ b/drivers/net/dsa/realtek/rtl8365mb_main.c
@@ -89,6 +89,12 @@
* things will work out-of-the-box for other chips, and a careful review of the
* vendor driver may be needed to expand support. The RTL8365MB-VC seems to be
* one of the simpler chips.
+ *
+ * The RTL8367S-VB (chip ID 0x6642) is not part of the family listed above. It
+ * belongs to a newer generation, which this driver calls family D. Its
+ * registers differ in the VLAN table, the external interface speed and RGMII
+ * configuration and the SerDes, so the code paths specific to it are selected
+ * with rtl8365mb_get_family().
*/
#include <linux/bitfield.h>
@@ -120,9 +126,10 @@
#define RTL8365MB_NUM_PHYREGS 32
#define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1)
#define RTL8365MB_MAX_NUM_PORTS 11
-/* Valid for the whole family except RTL8370B, which has 4160 entries.
- * RTL8370B is mentioned in vendor code but it might not even belong
- * to the same RTL8367C family.
+#define RTL8365MB_D_MAX_NUM_PORTS 8
+/* Valid for the whole RTL8367C family (and for family D, RTL8367S-VB)
+ * except RTL8370B, which has 4160 entries. RTL8370B is mentioned in
+ * vendor code but it might not even belong to the same RTL8367C family.
*/
#define RTL8365MB_LEARN_LIMIT_MAX 2112
#define RTL8365MB_MAX_NUM_EXTINTS 3
@@ -895,6 +902,19 @@ static const struct rtl8365mb_chip_info rtl8365mb_chip_infos[] = {
.jam_table = rtl8365mb_init_jam_8365mb_vc,
.jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc),
},
+ {
+ .name = "RTL8367S-VB",
+ .chip_id = 0x6642,
+ .chip_ver = 0x0010,
+ .family = RTL8365MB_FAMILY_D,
+ .extints = {
+ { 6, 0, PHY_INTF(SGMII) | PHY_INTF(HSGMII) },
+ { 7, 1, PHY_INTF(MII) | PHY_INTF(TMII) |
+ PHY_INTF(RMII) | PHY_INTF(RGMII) },
+ },
+ .jam_table = rtl8365mb_init_jam_8365mb_vc,
+ .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc),
+ },
};
enum rtl8365mb_stp_state {
@@ -3996,7 +4016,11 @@ static int rtl8365mb_detect(struct realtek_priv *priv)
dev_info(priv->dev, "found an %s switch\n", mb->chip_info->name);
- priv->num_ports = RTL8365MB_MAX_NUM_PORTS;
+ if (rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D)
+ priv->num_ports = RTL8365MB_D_MAX_NUM_PORTS;
+ else
+ priv->num_ports = RTL8365MB_MAX_NUM_PORTS;
+
mb->priv = priv;
ret = devm_mutex_init(priv->dev, &mb->sds_lock);
--
2.53.0
^ permalink raw reply [flat|nested] 11+ messages in thread