Re: [PATCH DNM v3 8/8] arm64: dts: qcom: kaanapali: Add MPAM MSC nodes for the L2 caches

[Yin Li <yin.li@oss.qualcomm.com>]

On 10/9/2026 5:00 AM, Rob Herring wrote:
> On Thu, Oct 08, 2026 at 02:41:17PM +0800, Yin Li wrote:
>> Add an MPAM MSC device node for each L2 cache. Each MSC is nested
>> directly under its L2 cache node so that the cache node is the MSC's
>> parent device and its CPU affinity is derived from that cache.
>>
>> The L2 cache nodes are placed directly under the root node. The root is
>> the root of the physical address space, so each cache node only needs an
>> identity 'ranges' property for its nested MSC's 'reg' to be resolved to
>> a physical address. The two caches use distinct node names (l2-cache-0
>> and l2-cache-1) since a cache node has no MMIO unit-address of its own.
>>
>> The nodes are disabled by default. Production firmware does not expose
>> MSC register access to the OS, so these nodes can only be enabled on a
>> local test setup where firmware permits direct MMIO access to the MSCs.
>> This DTS is therefore only an example for other platform DT authors and
>> is not intended to be merged.
>>
>> Co-developed-by: Huang Yiwei <huang.yiwei@oss.qualcomm.com>
>> Signed-off-by: Huang Yiwei <huang.yiwei@oss.qualcomm.com>
>> Signed-off-by: Yin Li <yin.li@oss.qualcomm.com>
>> ---
>>   arch/arm64/boot/dts/qcom/kaanapali.dtsi | 50 +++++++++++++++++++++++++--------
>>   1 file changed, 38 insertions(+), 12 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>> index 131fd2a16c54..b1dcb1e9c570 100644
>> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>> @@ -48,12 +48,6 @@ cpu0: cpu@0 {
>>   			power-domains = <&cpu_pd0>, <&scmi_perf 0>;
>>   			power-domain-names = "psci", "perf";
>>   			#cooling-cells = <2>;
>> -
>> -			l2_0: l2-cache {
>> -				compatible = "cache";
>> -				cache-level = <2>;
>> -				cache-unified;
>> -			};
>>   		};
>>   
>>   		cpu1: cpu@100 {
>> @@ -120,12 +114,6 @@ cpu6: cpu@10000 {
>>   			power-domains = <&cpu_pd6>, <&scmi_perf 1>;
>>   			power-domain-names = "psci", "perf";
>>   			#cooling-cells = <2>;
>> -
>> -			l2_1: l2-cache {
>> -				compatible = "cache";
>> -				cache-level = <2>;
>> -				cache-unified;
>> -			};
>>   		};
>>   
>>   		cpu7: cpu@10100 {
>> @@ -531,6 +519,44 @@ soccp_smp2p_in: slave-kernel {
>>   		};
>>   	};
>>   
>> +	l2_0: l2-cache-0 {
> 
> cache@19870000
> 

Hi Rob,

Thanks for review.

Good point, Will update on next version.

>> +		compatible = "cache";
> 
> You need a specific compatible here for your implementation.
> 

Will add a vendor-specific compatible:"qcom,kaanapali-l2-cache", "cache".

>> +		cache-level = <2>;
>> +		cache-unified;
>> +		cache-size = <0xc00000>;
>> +		ranges;
> 
> Are there any other registers for the cache other than the MSC? If not,
> then:
> 
> ranges = <0x0 0x19870000 0x10000>;
> 
> If there are, you need 'reg' here.
> 

There are no other registers under the cache node besides the MSC.
Will update ranges and the MSC reg accordingly.

>> +
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
> 
> You don't need 64 bits of address and size here.
> 

Agreed, will drop to #address-cells = <1> and #size-cells = <1>.

>> +
>> +		msc@19870000 {
>> +			compatible = "arm,mpam-msc";
>> +			reg = <0x0 0x19870000 0x0 0x10000>;
> 
> The MPAM register length is 0x321C.
> 

You are right, the MPAM register space is 0x321c per the specification.
Will update accordingly.

Thanks,
Yin

> Rob

-- 
Thx and BRs,
Yin