Re: [PATCH v3 3/8] dt-bindings: arm: Add MPAM MSC binding

[Yin Li <yin.li@oss.qualcomm.com>]

On 10/12/2026 3:05 PM, Yin Li wrote:
> 
> 
> On 10/9/2026 5:27 AM, Rob Herring wrote:
>> On Thu, Oct 08, 2026 at 02:41:12PM +0800, Yin Li wrote:
>>> From: Rob Herring <robh@kernel.org>
>>>
>>> The binding is designed around the assumption that an MSC will be a
>>> sub-block of something else such as a memory controller, cache 
>>> controller,
>>> or IOMMU. However, it's certainly possible a design does not have that
>>> association or has a mixture of both, so the binding illustrates how 
>>> we can
>>> support that with RIS child nodes.
>>>
>>> A key part of MPAM is we need to know about all of the MSCs in the 
>>> system
>>> before it can be enabled. This drives the need for the genericish
>>> 'arm,mpam-msc' compatible. Though we can't assume an MSC is accessible
>>> until a h/w specific driver potentially enables the h/w.
>>>
>>> Cc: James Morse <james.morse@arm.com>
>>> Signed-off-by: Rob Herring <robh@kernel.org>
>>> Signed-off-by: James Morse <james.morse@arm.com>
>>> [ Yin Li and Huang Yiwei: use oneOf for the compatible to allow both
>>>    standalone arm,mpam-msc and the two-item combination; fix schema 
>>> field
>>>    order, type constraints and yamllint spacing; fix example reg 
>>> addresses,
>>>    add arm,mpam-device phandle and remove TODO comment ]
>>> Co-developed-by: Huang Yiwei <huang.yiwei@oss.qualcomm.com>
>>> Signed-off-by: Huang Yiwei <huang.yiwei@oss.qualcomm.com>
>>> Signed-off-by: Yin Li <yin.li@oss.qualcomm.com>
>>> ---
>>>   .../devicetree/bindings/arm/arm,mpam-msc.yaml      | 202 ++++++++++ 
>>> +++++++++++
>>>   1 file changed, 202 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/arm,mpam-msc.yaml 
>>> b/Documentation/devicetree/bindings/arm/arm,mpam-msc.yaml
>>> new file mode 100644
>>> index 000000000000..3c7b13a23ff2
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/arm/arm,mpam-msc.yaml
>>> @@ -0,0 +1,202 @@
>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/arm/arm,mpam-msc.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Arm Memory System Resource Partitioning and Monitoring (MPAM)
>>> +
>>> +maintainers:
>>> +  - Rob Herring <robh@kernel.org>
>>> +
>>> +description: |
>>> +  The Arm MPAM specification can be found here:
>>> +
>>> +  https://developer.arm.com/documentation/ddi0598/latest
>>> +
>>> +properties:
>>> +  compatible:
>>> +    oneOf:
>>> +      - const: arm,mpam-msc                   # Further details are 
>>> discoverable
>>> +      - items:
>>> +          - const: arm,mpam-memory-controller-msc
>>
>> Why do we need this?
>>
> 
> Hi Rob,
> 
> Thanks for the review.
> 
> The 'arm,mpam-memory-controller-msc' compatible is needed because,
> unlike cache MSCs, memory controller MSCs cannot rely on the parent node
> to identify the resource type.
> 
> Cache controllers universally carry a 'cache' compatible, so the driver
> can recognise any cache parent and derive the cache ID from standard
> properties. No equivalent convention exists for memory controllers, and
> the component ID comes from the MSC's own 'numa-node-id' rather than the
> parent, so there is no parent attribute to rely on.
> 

Hi Rob,

As a follow-up to my previous reply:
Whatever the outcome of the discussion on "arm_mpam: Add support for
memory controller MSC on DT platforms", we will keep the binding and
driver support consistent. If it's dropped, the 
'arm,mpam-memory-controller-msc' compatible, 'numa-node-id' property, 
and the memory controller example will be removed together.

Thanks,
Yin


> 'arm,mpam-memory-controller-msc' provides the explicit declaration that
> this MSC controls memory. It is used in "arm_mpam: Add support for
> memory controller MSC on DT platforms".
> 
> On 'oneOf': the original 'items' form requires both strings to be
> present, which is not appropriate for cache MSCs. Andre also noted this 
> in RFC v2, so we changed it to 'oneOf'.
> 
>>> +          - const: arm,mpam-msc
>>> +
>>> +  reg:
>>> +    maxItems: 1
>>> +    description: A memory region containing registers as defined in 
>>> the MPAM
>>> +      specification.
>>> +
>>> +  interrupts:
>>> +    minItems: 1
>>> +    items:
>>> +      - description: error (optional)
>>> +      - description: overflow (optional, only for monitoring)
>>> +
>>> +  interrupt-names:
>>> +    oneOf:
>>> +      - items:
>>> +          - enum: [error, overflow]
>>> +      - items:
>>> +          - const: error
>>> +          - const: overflow
>>
>> This can be expressed as:
>>
>>        minItems: 1
>>        items:
>>          - enum: [error, overflow]
>>          - const: overflow
>>
> 
> Agreed, will update.
> 
>>> +
>>> +  arm,not-ready-us:
>>> +    description: The maximum time in microseconds for monitoring 
>>> data to be
>>> +      accurate after a settings change. For more information, see the
>>> +      Not-Ready (NRDY) bit description in the MPAM specification.
>>> +
>>> +  numa-node-id:
>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>> +    description: NUMA node identifier for the memory resource this 
>>> MSC controls.
>>> +
>>> +  '#address-cells':
>>> +    const: 1
>>> +
>>> +  '#size-cells':
>>> +    const: 0
>>> +
>>> +patternProperties:
>>> +  '^ris@[0-9a-f]+$':
>>
>> Based on the 'reg' constraints, drop the '+'.
> 
> Agreed, will update.
> 
>>
>>> +    type: object
>>> +    additionalProperties: false
>>> +    description:
>>> +      RIS nodes for each resource instance in an MSC. These nodes 
>>> are required
>>> +      for each resource instance implementing known MPAM controls
>>> +
>>> +    properties:
>>> +      compatible:
>>> +        enum:
>>> +          - arm,mpam-cache
>>> +          # Memory bandwidth
>>> +          - arm,mpam-memory
>>> +
>>> +      reg:
>>> +        minimum: 0
>>> +        maximum: 0xf
>>> +
>>> +      cpus:
>>> +        $ref: /schemas/types.yaml#/definitions/phandle-array
>>
>> Drop. 'cpus' has a type already.
>>
> 
> Agreed, will update.
> 
>>> +        description:
>>> +          Phandle(s) to the CPU node(s) this RIS belongs to. By 
>>> default, the
>>> +          parent device's affinity is used.
>>> +
>>> +      arm,mpam-device:
>>> +        $ref: /schemas/types.yaml#/definitions/phandle
>>> +        description:
>>> +          By default, the MPAM enabled device associated with a RIS 
>>> is the MSC's
>>> +          parent node. It is possible for each RIS to be associated 
>>> with
>>> +          different devices in which case 'arm,mpam-device' should 
>>> be used.
>>
>> We should drop this until there's a use for it.
>>
> 
> On 'arm,mpam-device': we believe this property is structurally
> necessary. The MPAM specification (IHI0099B) states:
>      "Resource instance selection (RIS) allows an MPAM MSC to support
>      multiple resources, including multiple resources using the same
>      resource type or partitioning control. When RIS is implemented, an
>      MPAM MSC must implement independent resource controls and two or
>      more resources of the same type."
> 
> Once an MSC implements RIS, it must support ≥ 2 resources of the same
> type (a spec requirement). An MSC node has only one parent, so the
> association between each RIS and its corresponding device cannot be
> expressed through a shared parent alone. A per-RIS explicit association
> mechanism is therefore needed, and 'arm,mpam-device' is designed for
> exactly this purpose.
> 
> The property is used in the immediately following patch "arm_mpam: Add
> device tree support for MSC probing". If you have a different view on
> this design, we are happy to discuss further.
> 
> 
>>> +
>>> +    required:
>>> +      - compatible
>>> +      - reg
>>> +
>>> +required:
>>> +  - compatible
>>> +  - reg
>>> +
>>> +dependencies:
>>> +  interrupts: [interrupt-names]
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> +  - |
>>> +    L3: cache-controller@30000000 {
>>> +        compatible = "foo,a-l3-cache", "cache";
>>> +        cache-level = <3>;
>>> +        cache-unified;
>>> +
>>> +        ranges = <0x0 0x30000000 0x800000>;
>>> +        #address-cells = <1>;
>>> +        #size-cells = <1>;
>>> +
>>> +        msc@10000 {
>>> +            compatible = "arm,mpam-msc";
>>> +            reg = <0x10000 0x2000>;
>>> +            interrupts = <1>, <2>;
>>> +            interrupt-names = "error", "overflow";
>>> +            arm,not-ready-us = <1>;
>>> +            /* CPU affinity implied by parent cache node  */
>>> +        };
>>> +    };
>>> +
>>> +    mem: memory-controller@20000 {
>>> +        compatible = "foo,a-memory-controller";
>>> +        reg = <0x20000 0x1000>;
>>> +
>>> +        #address-cells = <1>;
>>> +        #size-cells = <1>;
>>> +        ranges;
>>> +
>>> +        msc@21000 {
>>> +            compatible = "arm,mpam-memory-controller-msc", 
>>> "arm,mpam-msc";
>>> +            reg = <0x21000 0x1000>;
>>> +            interrupts = <3>;
>>> +            interrupt-names = "error";
>>> +            arm,not-ready-us = <1>;
>>> +            numa-node-id = <1>;
>>> +        };
>>> +    };
>>> +
>>> +    iommu@40000 {
>>> +        reg = <0x40000 0x1000>;
>>> +
>>> +        ranges;
>>> +        #address-cells = <1>;
>>> +        #size-cells = <1>;
>>> +
>>> +        msc@41000 {
>>> +            compatible = "arm,mpam-msc";
>>> +            reg = <0x41000 0x1000>;
>>> +            interrupts = <5>, <6>;
>>> +            interrupt-names = "error", "overflow";
>>> +            arm,not-ready-us = <1>;
>>> +
>>> +            #address-cells = <1>;
>>> +            #size-cells = <0>;
>>> +
>>> +            ris@2 {
>>> +                compatible = "arm,mpam-cache";
>>> +                reg = <2>;
>>> +                arm,mpam-device = <&L3>;
>>> +            };
>>> +        };
>>> +    };
>>> +
>>> +    msc@80000 {
>>> +        compatible = "foo,a-standalone-msc";
>>> +        reg = <0x80000 0x1000>;
>>> +
>>> +        clocks = <&clks 123>;
>>> +
>>> +        ranges;
>>> +        #address-cells = <1>;
>>> +        #size-cells = <1>;
>>> +
>>> +        msc@10000 {
>>> +            compatible = "arm,mpam-msc";
>>> +            reg = <0x10000 0x2000>;
>>> +            interrupts = <7>;
>>> +            interrupt-names = "overflow";
>>> +            arm,not-ready-us = <1>;
>>> +
>>> +            #address-cells = <1>;
>>> +            #size-cells = <0>;
>>> +
>>> +            ris@0 {
>>> +                compatible = "arm,mpam-cache";
>>> +                reg = <0>;
>>> +                arm,mpam-device = <&L2_0>;
>>> +            };
>>> +
>>> +            ris@1 {
>>> +                compatible = "arm,mpam-memory";
>>> +                reg = <1>;
>>> +                arm,mpam-device = <&mem>;
>>> +            };
>>> +        };
>>> +    };
>>> +
>>> +...
>>>
>>> -- 
>>> 2.34.1
>>>
> 

-- 
Thx and BRs,
Yin