* [PATCH v3 1/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5
2025-11-20 17:33 [PATCH v3 0/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5 Krzysztof Kozlowski
@ 2025-11-20 17:33 ` Krzysztof Kozlowski
2026-01-05 17:51 ` Taniya Das
2025-11-20 17:33 ` [PATCH v3 2/3] arm64: dts: qcom: sm8750-mtp: Enable Iris codec Krzysztof Kozlowski
` (2 subsequent siblings)
3 siblings, 1 reply; 6+ messages in thread
From: Krzysztof Kozlowski @ 2025-11-20 17:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Krzysztof Kozlowski,
Krzysztof Kozlowski
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Add Iris video codec to SM8750 SoC, which comes with significantly
different powering up sequence than previous SM8650, thus different
clocks and resets. For consistency keep existing clock and clock-names
naming, so the list shares common part.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
Keeping my original authorship (with bouncing email) + new SoB. There
were no changes here done under korg identity, so all credits are for
Linaro.
---
arch/arm64/boot/dts/qcom/sm8750.dtsi | 119 +++++++++++++++++++++++++++++++++++
1 file changed, 119 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 3f0b57f428bb..f8f6cbcf7f45 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8750-gcc.h>
#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
+#include <dt-bindings/clock/qcom,sm8750-videocc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
@@ -2740,6 +2741,124 @@ usb_dwc3_ss: endpoint {
};
};
+ iris: video-codec@aa00000 {
+ compatible = "qcom,sm8750-iris";
+ reg = <0x0 0x0aa00000 0x0 0xf0000>;
+
+ clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+ <&videocc VIDEO_CC_MVS0C_CLK>,
+ <&videocc VIDEO_CC_MVS0_CLK>,
+ <&gcc GCC_VIDEO_AXI1_CLK>,
+ <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>,
+ <&videocc VIDEO_CC_MVS0_FREERUN_CLK>;
+ clock-names = "iface",
+ "core",
+ "vcodec0_core",
+ "iface1",
+ "core_freerun",
+ "vcodec0_core_freerun";
+
+ dma-coherent;
+ iommus = <&apps_smmu 0x1940 0>,
+ <&apps_smmu 0x1947 0>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cpu-cfg",
+ "video-mem";
+
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ memory-region = <&video_mem>;
+
+ operating-points-v2 = <&iris_opp_table>;
+
+ power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
+ <&videocc VIDEO_CC_MVS0_GDSC>,
+ <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_MMCX>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "mxc",
+ "mmcx";
+
+ resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
+ <&gcc GCC_VIDEO_AXI1_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>;
+ reset-names = "bus0",
+ "bus1",
+ "core",
+ "vcodec0_core";
+
+ /*
+ * IRIS firmware is signed by vendors, only
+ * enable in boards where the proper signed firmware
+ * is available.
+ */
+ status = "disabled";
+
+ iris_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-240000000 {
+ opp-hz = /bits/ 64 <240000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>,
+ <&rpmhpd_opp_low_svs_d1>;
+ };
+
+ opp-338000000 {
+ opp-hz = /bits/ 64 <338000000>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-420000000 {
+ opp-hz = /bits/ 64 <420000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+
+ opp-444000000 {
+ opp-hz = /bits/ 64 <444000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-533333334 {
+ opp-hz = /bits/ 64 <533333334>;
+ required-opps = <&rpmhpd_opp_nom>,
+ <&rpmhpd_opp_nom>;
+ };
+
+ opp-570000000 {
+ opp-hz = /bits/ 64 <570000000>;
+ required-opps = <&rpmhpd_opp_nom_l1>,
+ <&rpmhpd_opp_nom_l1>;
+ };
+
+ opp-630000000 {
+ opp-hz = /bits/ 64 <630000000>;
+ required-opps = <&rpmhpd_opp_turbo>,
+ <&rpmhpd_opp_turbo>;
+ };
+ };
+ };
+
+ videocc: clock-controller@aaf0000 {
+ compatible = "qcom,sm8750-videocc";
+ reg = <0x0 0x0aaf0000 0x0 0x10000>;
+ clocks = <&bi_tcxo_div2>,
+ <&gcc GCC_VIDEO_AHB_CLK>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8750-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>;
--
2.48.1
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v3 0/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5
2025-11-20 17:33 [PATCH v3 0/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5 Krzysztof Kozlowski
` (2 preceding siblings ...)
2025-11-20 17:33 ` [PATCH v3 3/3] arm64: dts: qcom: sm8750-qrd: " Krzysztof Kozlowski
@ 2025-11-24 14:28 ` Rob Herring
3 siblings, 0 replies; 6+ messages in thread
From: Rob Herring @ 2025-11-24 14:28 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Andersson, Krzysztof Kozlowski, devicetree,
Krzysztof Kozlowski, linux-kernel, Konrad Dybcio, linux-arm-msm,
Conor Dooley
On Thu, 20 Nov 2025 18:33:30 +0100, Krzysztof Kozlowski wrote:
> Hi,
>
> Dependency - video-cc clocks bindings header - is already in qcom clk
> tree for v6.19:
> https://l re.kernel.org/r/20251118-sm8750-videocc-v2-v4-0-049882a70c9f@oss.qualcomm.com
>
> Changes in v3:
> - Add tags, update dependencies, rebase.
> - Add missing opp-570.
> - Link to v2: https://lore.kernel.org/r/20250806-b4-sm8750-iris-dts-v2-0-2ce197525eed@linaro.org
>
> Changes in v2:
> - Patch #1: Add RPMHPD_MXC (Konrad)
> - Link to v1: https://lore.kernel.org/r/20250714-b4-sm8750-iris-dts-v1-0-93629b246d2e@linaro.org
>
> Best regards,
> Krzysztof
>
> ---
> Krzysztof Kozlowski (3):
> arm64: dts: qcom: sm8750: Add Iris VPU v3.5
> arm64: dts: qcom: sm8750-mtp: Enable Iris codec
> arm64: dts: qcom: sm8750-qrd: Enable Iris codec
>
> arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 4 ++
> arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 4 ++
> arch/arm64/boot/dts/qcom/sm8750.dtsi | 119 ++++++++++++++++++++++++++++++++
> 3 files changed, 127 insertions(+)
> ---
> base-commit: 9eb88791f9759995910e9b96bb55a9cad54bb84a
> change-id: 20250714-b4-sm8750-iris-dts-ebdb5dc4ee27
>
> Best regards,
> --
> Krzysztof Kozlowski <krzk@kernel.org>
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
This patch series was applied (using b4) to base:
Base: base-commit 9eb88791f9759995910e9b96bb55a9cad54bb84a not known, ignoring
Base: attempting to guess base-commit...
Base: tags/next-20251120 (exact match)
Base: tags/next-20251120 (use --merge-base to override)
If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)
New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for 20251120-b4-sm8750-iris-dts-v3-0-8715442c30d9@kernel.org:
arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: clock-controller@aaf0000 (qcom,sm8750-videocc): 'required-opps' is a required property
from schema $id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml
arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: clock-controller@aaf0000 (qcom,sm8750-videocc): 'required-opps' is a required property
from schema $id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml
^ permalink raw reply [flat|nested] 6+ messages in thread