* [PATCH v16 0/3] reset: realtek: Add RTD1625 reset support
@ 2026-11-12 5:31 Yu-Chun Lin
2026-11-12 5:31 ` [PATCH v16 1/3] dt-bindings: reset: Add Realtek RTD1625 reset IDs Yu-Chun Lin
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Yu-Chun Lin @ 2026-11-12 5:31 UTC (permalink / raw)
To: p.zabel, robh, krzk+dt, conor+dt, cylee12
Cc: devicetree, linux-kernel, james.tai, cy.huang, stanley_chang,
eleanor.lin
Hi all,
This series adds reset controller support for the Realtek RTD1625 SoC.
Since the reset and clock controllers share the same register space, they
are now decoupled via the Auxiliary Bus framework. This allows the reset
drivers to be submitted as a separate series.
Best regards,
Yu-Chun Lin
---
Changes in v16:
- Split out the reset controller support from the previously combined
clock/reset series (v15) [1].
- Extract the reset IDs from the clock binding and introduce them as
a standalone patch (Patch 1).
- Add "REALTEK RESET DRIVERS" entry to the MAINTAINERS file.
- The driver code remains unchanged since v11 [2].
[1] https://lore.kernel.org/lkml/20261002074331.3066919-1-eleanor.lin@realtek.com/
[2] https://lore.kernel.org/lkml/20260728142806.1954638-1-eleanor.lin@realtek.com/
Cheng-Yu Lee (3):
dt-bindings: reset: Add Realtek RTD1625 reset IDs
reset: Add Realtek basic reset support
reset: realtek: Add RTD1625 reset controller driver
MAINTAINERS | 7 +
drivers/reset/Kconfig | 1 +
drivers/reset/Makefile | 1 +
drivers/reset/realtek/Kconfig | 19 ++
drivers/reset/realtek/Makefile | 3 +
drivers/reset/realtek/reset-rtd1625.c | 262 ++++++++++++++++++++
drivers/reset/realtek/reset-rtk-common.c | 73 ++++++
drivers/reset/realtek/reset-rtk-common.h | 29 +++
include/dt-bindings/reset/realtek,rtd1625.h | 171 +++++++++++++
9 files changed, 566 insertions(+)
create mode 100644 drivers/reset/realtek/Kconfig
create mode 100644 drivers/reset/realtek/Makefile
create mode 100644 drivers/reset/realtek/reset-rtd1625.c
create mode 100644 drivers/reset/realtek/reset-rtk-common.c
create mode 100644 drivers/reset/realtek/reset-rtk-common.h
create mode 100644 include/dt-bindings/reset/realtek,rtd1625.h
--
2.43.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v16 1/3] dt-bindings: reset: Add Realtek RTD1625 reset IDs 2026-11-12 5:31 [PATCH v16 0/3] reset: realtek: Add RTD1625 reset support Yu-Chun Lin @ 2026-11-12 5:31 ` Yu-Chun Lin 2026-11-12 9:08 ` Krzysztof Kozlowski 2026-11-12 9:10 ` Krzysztof Kozlowski 2026-11-12 5:31 ` [PATCH v16 2/3] reset: Add Realtek basic reset support Yu-Chun Lin ` (2 subsequent siblings) 3 siblings, 2 replies; 7+ messages in thread From: Yu-Chun Lin @ 2026-11-12 5:31 UTC (permalink / raw) To: p.zabel, robh, krzk+dt, conor+dt, cylee12 Cc: devicetree, linux-kernel, james.tai, cy.huang, stanley_chang, eleanor.lin From: Cheng-Yu Lee <cylee12@realtek.com> Add the device tree bindings header containing reset indices for the Realtek RTD1625 SoC. Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com> Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> --- MAINTAINERS | 6 + include/dt-bindings/reset/realtek,rtd1625.h | 171 ++++++++++++++++++++ 2 files changed, 177 insertions(+) create mode 100644 include/dt-bindings/reset/realtek,rtd1625.h diff --git a/MAINTAINERS b/MAINTAINERS index 93abbb315065..a47642615d59 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23551,6 +23551,12 @@ S: Maintained F: Documentation/devicetree/bindings/net/pse-pd/realtek,pse-mcu-gen1.yaml F: drivers/net/pse-pd/realtek-pse-mcu* +REALTEK RESET DRIVERS +M: Cheng-Yu Lee <cylee12@realtek.com> +M: Yu-Chun Lin <eleanor.lin@realtek.com> +S: Supported +F: include/dt-bindings/reset/realtek,rtd1625.h + REALTEK RTL83xx SMI DSA ROUTER CHIPS M: Linus Walleij <linusw@kernel.org> M: Luiz Angelo Daros de Luca <luizluca@gmail.com> diff --git a/include/dt-bindings/reset/realtek,rtd1625.h b/include/dt-bindings/reset/realtek,rtd1625.h new file mode 100644 index 000000000000..a906ab822f18 --- /dev/null +++ b/include/dt-bindings/reset/realtek,rtd1625.h @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2026 Realtek Semiconductor Corp. + */ + +#ifndef __DT_BINDINGS_RTK_RESET_RTD1625_H +#define __DT_BINDINGS_RTK_RESET_RTD1625_H + +#define RTD1625_CRT_RSTN_MISC 0 +#define RTD1625_CRT_RSTN_DIP 1 +#define RTD1625_CRT_RSTN_GSPI 2 +#define RTD1625_CRT_RSTN_SDS 3 +#define RTD1625_CRT_RSTN_SDS_REG 4 +#define RTD1625_CRT_RSTN_SDS_PHY 5 +#define RTD1625_CRT_RSTN_GPU2D 6 +#define RTD1625_CRT_RSTN_DC_PHY 7 +#define RTD1625_CRT_RSTN_DCPHY_CRT 8 +#define RTD1625_CRT_RSTN_LSADC 9 +#define RTD1625_CRT_RSTN_SE 10 +#define RTD1625_CRT_RSTN_DLA 11 +#define RTD1625_CRT_RSTN_JPEG 12 +#define RTD1625_CRT_RSTN_SD 13 +#define RTD1625_CRT_RSTN_SDIO 14 +#define RTD1625_CRT_RSTN_PCR_CNT 15 +#define RTD1625_CRT_RSTN_PCIE0_STITCH 16 +#define RTD1625_CRT_RSTN_PCIE0_PHY 17 +#define RTD1625_CRT_RSTN_PCIE0 18 +#define RTD1625_CRT_RSTN_PCIE0_CORE 19 +#define RTD1625_CRT_RSTN_PCIE0_POWER 20 +#define RTD1625_CRT_RSTN_PCIE0_NONSTICH 21 +#define RTD1625_CRT_RSTN_PCIE0_PHY_MDIO 22 +#define RTD1625_CRT_RSTN_PCIE0_SGMII_MDIO 23 +#define RTD1625_CRT_RSTN_VO2 24 +#define RTD1625_CRT_RSTN_MISC_SC0 25 +#define RTD1625_CRT_RSTN_MD 26 +#define RTD1625_CRT_RSTN_LVDS1 27 +#define RTD1625_CRT_RSTN_LVDS2 28 +#define RTD1625_CRT_RSTN_MISC_SC1 29 +#define RTD1625_CRT_RSTN_I2C_3 30 +#define RTD1625_CRT_RSTN_FAN 31 +#define RTD1625_CRT_RSTN_TVE 32 +#define RTD1625_CRT_RSTN_AIO 33 +#define RTD1625_CRT_RSTN_VO 34 +#define RTD1625_CRT_RSTN_MIPI_CSI 35 +#define RTD1625_CRT_RSTN_HDMIRX 36 +#define RTD1625_CRT_RSTN_HDMIRX_WRAP 37 +#define RTD1625_CRT_RSTN_HDMI 38 +#define RTD1625_CRT_RSTN_DISP 39 +#define RTD1625_CRT_RSTN_SATA_PHY_POW1 40 +#define RTD1625_CRT_RSTN_SATA_PHY_POW0 41 +#define RTD1625_CRT_RSTN_SATA_MDIO1 42 +#define RTD1625_CRT_RSTN_SATA_MDIO0 43 +#define RTD1625_CRT_RSTN_SATA_WRAP 44 +#define RTD1625_CRT_RSTN_SATA_MAC_P1 45 +#define RTD1625_CRT_RSTN_SATA_MAC_P0 46 +#define RTD1625_CRT_RSTN_SATA_MAC_COM 47 +#define RTD1625_CRT_RSTN_PCIE1_STITCH 48 +#define RTD1625_CRT_RSTN_PCIE1_PHY 49 +#define RTD1625_CRT_RSTN_PCIE1 50 +#define RTD1625_CRT_RSTN_PCIE1_CORE 51 +#define RTD1625_CRT_RSTN_PCIE1_POWER 52 +#define RTD1625_CRT_RSTN_PCIE1_NONSTICH 53 +#define RTD1625_CRT_RSTN_PCIE1_PHY_MDIO 54 +#define RTD1625_CRT_RSTN_HDMITOP 55 +#define RTD1625_CRT_RSTN_I2C_4 56 +#define RTD1625_CRT_RSTN_I2C_5 57 +#define RTD1625_CRT_RSTN_TSIO 58 +#define RTD1625_CRT_RSTN_VI 59 +#define RTD1625_CRT_RSTN_EDP 60 +#define RTD1625_CRT_RSTN_VE1_MMU 61 +#define RTD1625_CRT_RSTN_VE1_MMU_FUNC 62 +#define RTD1625_CRT_RSTN_HSE_MMU 63 +#define RTD1625_CRT_RSTN_HSE_MMU_FUNC 64 +#define RTD1625_CRT_RSTN_MDLM2M 65 +#define RTD1625_CRT_RSTN_ISO_GSPI 66 +#define RTD1625_CRT_RSTN_SOFT_NPU 67 +#define RTD1625_CRT_RSTN_SPI2EMMC 68 +#define RTD1625_CRT_RSTN_EARC 69 +#define RTD1625_CRT_RSTN_VE1 70 +#define RTD1625_CRT_RSTN_PCIE2_STITCH 71 +#define RTD1625_CRT_RSTN_PCIE2_PHY 72 +#define RTD1625_CRT_RSTN_PCIE2 73 +#define RTD1625_CRT_RSTN_PCIE2_CORE 74 +#define RTD1625_CRT_RSTN_PCIE2_POWER 75 +#define RTD1625_CRT_RSTN_PCIE2_NONSTICH 76 +#define RTD1625_CRT_RSTN_PCIE2_PHY_MDIO 77 +#define RTD1625_CRT_RSTN_DCPHY_UMCTL2 78 +#define RTD1625_CRT_RSTN_MIPI_DSI 79 +#define RTD1625_CRT_RSTN_HIFM 80 +#define RTD1625_CRT_RSTN_NSRAM 81 +#define RTD1625_CRT_RSTN_AUCPU0_REG 82 +#define RTD1625_CRT_RSTN_MDL_GENPW 83 +#define RTD1625_CRT_RSTN_MDL_CHIP 84 +#define RTD1625_CRT_RSTN_MDL_IP 85 +#define RTD1625_CRT_RSTN_TEST_MUX 86 +#define RTD1625_CRT_RSTN_ISO_BIST 87 +#define RTD1625_CRT_RSTN_MAIN_BIST 88 +#define RTD1625_CRT_RSTN_MAIN2_BIST 89 +#define RTD1625_CRT_RSTN_VE1_BIST 90 +#define RTD1625_CRT_RSTN_VE2_BIST 91 +#define RTD1625_CRT_RSTN_DCPHY_BIST 92 +#define RTD1625_CRT_RSTN_GPU_BIST 93 +#define RTD1625_CRT_RSTN_DISP_BIST 94 +#define RTD1625_CRT_RSTN_NPU_BIST 95 +#define RTD1625_CRT_RSTN_CAS_BIST 96 +#define RTD1625_CRT_RSTN_VE4_BIST 97 +#define RTD1625_CRT_RSTN_EMMC 98 +#define RTD1625_CRT_RSTN_GPU 99 +#define RTD1625_CRT_RSTN_VE2 100 +#define RTD1625_CRT_RSTN_UR1 101 +#define RTD1625_CRT_RSTN_UR2 102 +#define RTD1625_CRT_RSTN_UR3 103 +#define RTD1625_CRT_RSTN_UR4 104 +#define RTD1625_CRT_RSTN_UR5 105 +#define RTD1625_CRT_RSTN_UR6 106 +#define RTD1625_CRT_RSTN_UR7 107 +#define RTD1625_CRT_RSTN_UR8 108 +#define RTD1625_CRT_RSTN_UR9 109 +#define RTD1625_CRT_RSTN_UR_TOP 110 +#define RTD1625_CRT_RSTN_I2C_7 111 +#define RTD1625_CRT_RSTN_I2C_6 112 +#define RTD1625_CRT_RSTN_SPI0 113 +#define RTD1625_CRT_RSTN_SPI1 114 +#define RTD1625_CRT_RSTN_SPI2 115 +#define RTD1625_CRT_RSTN_LSADC0 116 +#define RTD1625_CRT_RSTN_LSADC1 117 +#define RTD1625_CRT_RSTN_ISOMIS_DMA 118 +#define RTD1625_CRT_RSTN_AUDIO_ADC 119 +#define RTD1625_CRT_RSTN_DPTX 120 +#define RTD1625_CRT_RSTN_AUCPU1_REG 121 +#define RTD1625_CRT_RSTN_EDPTX 122 + +/* ISO reset */ +#define RTD1625_ISO_RSTN_VFD 0 +#define RTD1625_ISO_RSTN_CEC0 1 +#define RTD1625_ISO_RSTN_CEC1 2 +#define RTD1625_ISO_RSTN_CBUSTX 3 +#define RTD1625_ISO_RSTN_CBUSRX 4 +#define RTD1625_ISO_RSTN_USB3_PHY2_XTAL_POW 5 +#define RTD1625_ISO_RSTN_UR0 6 +#define RTD1625_ISO_RSTN_GMAC 7 +#define RTD1625_ISO_RSTN_GPHY 8 +#define RTD1625_ISO_RSTN_I2C_0 9 +#define RTD1625_ISO_RSTN_I2C_1 10 +#define RTD1625_ISO_RSTN_CBUS 11 +#define RTD1625_ISO_RSTN_USB_DRD 12 +#define RTD1625_ISO_RSTN_USB_HOST 13 +#define RTD1625_ISO_RSTN_USB_PHY_0 14 +#define RTD1625_ISO_RSTN_USB_PHY_1 15 +#define RTD1625_ISO_RSTN_USB_PHY_2 16 +#define RTD1625_ISO_RSTN_USB 17 +#define RTD1625_ISO_RSTN_TYPE_C 18 +#define RTD1625_ISO_RSTN_USB_U3_HOST 19 +#define RTD1625_ISO_RSTN_USB3_PHY0_POW 20 +#define RTD1625_ISO_RSTN_USB3_P0_MDIO 21 +#define RTD1625_ISO_RSTN_USB3_PHY1_POW 22 +#define RTD1625_ISO_RSTN_USB3_P1_MDIO 23 +#define RTD1625_ISO_RSTN_VTC 24 +#define RTD1625_ISO_RSTN_USB3_PHY2_POW 25 +#define RTD1625_ISO_RSTN_USB3_P2_MDIO 26 +#define RTD1625_ISO_RSTN_USB_PHY_3 27 +#define RTD1625_ISO_RSTN_USB_PHY_4 28 + +/* ISO_S reset */ +#define RTD1625_ISO_S_RSTN_ISOM_MIS 0 +#define RTD1625_ISO_S_RSTN_GPIOM 1 +#define RTD1625_ISO_S_RSTN_TIMER7 2 +#define RTD1625_ISO_S_RSTN_IRDA 3 +#define RTD1625_ISO_S_RSTN_UR10 4 + +#endif /* __DT_BINDINGS_RTK_RESET_RTD1625_H */ -- 2.43.0 ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v16 1/3] dt-bindings: reset: Add Realtek RTD1625 reset IDs 2026-11-12 5:31 ` [PATCH v16 1/3] dt-bindings: reset: Add Realtek RTD1625 reset IDs Yu-Chun Lin @ 2026-11-12 9:08 ` Krzysztof Kozlowski 2026-11-12 9:10 ` Krzysztof Kozlowski 1 sibling, 0 replies; 7+ messages in thread From: Krzysztof Kozlowski @ 2026-11-12 9:08 UTC (permalink / raw) To: Yu-Chun Lin Cc: p.zabel, robh, krzk+dt, conor+dt, cylee12, devicetree, linux-kernel, james.tai, cy.huang, stanley_chang On Thu, Nov 12, 2026 at 01:31:26PM +0800, Yu-Chun Lin wrote: > From: Cheng-Yu Lee <cylee12@realtek.com> > > Add the device tree bindings header containing reset indices for the > Realtek RTD1625 SoC. > > Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com> > Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com> > Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> > --- Here on in changelog you explain why there is no DT binding schema for this. Or where is it... Best regards, Krzysztof ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v16 1/3] dt-bindings: reset: Add Realtek RTD1625 reset IDs 2026-11-12 5:31 ` [PATCH v16 1/3] dt-bindings: reset: Add Realtek RTD1625 reset IDs Yu-Chun Lin 2026-11-12 9:08 ` Krzysztof Kozlowski @ 2026-11-12 9:10 ` Krzysztof Kozlowski 1 sibling, 0 replies; 7+ messages in thread From: Krzysztof Kozlowski @ 2026-11-12 9:10 UTC (permalink / raw) To: Yu-Chun Lin Cc: p.zabel, robh, krzk+dt, conor+dt, cylee12, devicetree, linux-kernel, james.tai, cy.huang, stanley_chang On Thu, Nov 12, 2026 at 01:31:26PM +0800, Yu-Chun Lin wrote: > From: Cheng-Yu Lee <cylee12@realtek.com> > > Add the device tree bindings header containing reset indices for the > Realtek RTD1625 SoC. > > Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com> > Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com> > Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> > --- > MAINTAINERS | 6 + > include/dt-bindings/reset/realtek,rtd1625.h | 171 ++++++++++++++++++++ > 2 files changed, 177 insertions(+) > create mode 100644 include/dt-bindings/reset/realtek,rtd1625.h > I need to go to the driver to see there are no bindings there... Make it easy and obvious for the reviewers next time. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v16 2/3] reset: Add Realtek basic reset support 2026-11-12 5:31 [PATCH v16 0/3] reset: realtek: Add RTD1625 reset support Yu-Chun Lin 2026-11-12 5:31 ` [PATCH v16 1/3] dt-bindings: reset: Add Realtek RTD1625 reset IDs Yu-Chun Lin @ 2026-11-12 5:31 ` Yu-Chun Lin 2026-11-12 5:31 ` [PATCH v16 3/3] reset: realtek: Add RTD1625 reset controller driver Yu-Chun Lin 2026-11-12 9:41 ` [PATCH v16 0/3] reset: realtek: Add RTD1625 reset support Philipp Zabel 3 siblings, 0 replies; 7+ messages in thread From: Yu-Chun Lin @ 2026-11-12 5:31 UTC (permalink / raw) To: p.zabel, robh, krzk+dt, conor+dt, cylee12 Cc: devicetree, linux-kernel, james.tai, cy.huang, stanley_chang, eleanor.lin From: Cheng-Yu Lee <cylee12@realtek.com> Define the common reset operations backed by a regmap-based register interface for Realtek SoCs. This library exports the standard reset control operations (assert, deassert, and status) to be utilized by other specific Realtek reset drivers. The implementation supports handling an optional write-enable bit required by certain Realtek reset controllers. Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com> Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> --- MAINTAINERS | 1 + drivers/reset/Kconfig | 1 + drivers/reset/Makefile | 1 + drivers/reset/realtek/Kconfig | 8 +++ drivers/reset/realtek/Makefile | 2 + drivers/reset/realtek/reset-rtk-common.c | 73 ++++++++++++++++++++++++ drivers/reset/realtek/reset-rtk-common.h | 29 ++++++++++ 7 files changed, 115 insertions(+) create mode 100644 drivers/reset/realtek/Kconfig create mode 100644 drivers/reset/realtek/Makefile create mode 100644 drivers/reset/realtek/reset-rtk-common.c create mode 100644 drivers/reset/realtek/reset-rtk-common.h diff --git a/MAINTAINERS b/MAINTAINERS index a47642615d59..f00f6e921246 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23555,6 +23555,7 @@ REALTEK RESET DRIVERS M: Cheng-Yu Lee <cylee12@realtek.com> M: Yu-Chun Lin <eleanor.lin@realtek.com> S: Supported +F: drivers/reset/realtek/* F: include/dt-bindings/reset/realtek,rtd1625.h REALTEK RTL83xx SMI DSA ROUTER CHIPS diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index eda9c698a95f..eda8f42954f2 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -452,6 +452,7 @@ config RESET_ZYNQMP source "drivers/reset/amlogic/Kconfig" source "drivers/reset/hisilicon/Kconfig" +source "drivers/reset/realtek/Kconfig" source "drivers/reset/spacemit/Kconfig" source "drivers/reset/starfive/Kconfig" source "drivers/reset/sti/Kconfig" diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 489fafd6bbe3..486a8d0048ac 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -2,6 +2,7 @@ obj-y += core.o obj-y += amlogic/ obj-y += hisilicon/ +obj-y += realtek/ obj-y += spacemit/ obj-y += starfive/ obj-y += sti/ diff --git a/drivers/reset/realtek/Kconfig b/drivers/reset/realtek/Kconfig new file mode 100644 index 000000000000..5ddf8e5c09c7 --- /dev/null +++ b/drivers/reset/realtek/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only +config RESET_RTK_COMMON + tristate "Realtek common reset driver" if COMPILE_TEST + help + This option enables the common reset controller library for + Realtek SoCs. It provides shared reset control operations + (assert, deassert, status) that other Realtek-specific reset + drivers can use. diff --git a/drivers/reset/realtek/Makefile b/drivers/reset/realtek/Makefile new file mode 100644 index 000000000000..6d68e41748bf --- /dev/null +++ b/drivers/reset/realtek/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_RESET_RTK_COMMON) += reset-rtk-common.o diff --git a/drivers/reset/realtek/reset-rtk-common.c b/drivers/reset/realtek/reset-rtk-common.c new file mode 100644 index 000000000000..6900932b0a32 --- /dev/null +++ b/drivers/reset/realtek/reset-rtk-common.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019-2026 Realtek Semiconductor Corporation + */ + +#include <linux/export.h> +#include <linux/module.h> +#include <linux/regmap.h> +#include "reset-rtk-common.h" + +static inline struct rtk_reset_data *to_rtk_reset_controller(struct reset_controller_dev *r) +{ + return container_of(r, struct rtk_reset_data, rcdev); +} + +static inline const struct rtk_reset_desc *rtk_reset_get_desc(struct rtk_reset_data *data, + unsigned long idx) +{ + return &data->descs[idx]; +} + +static int rtk_reset_assert(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct rtk_reset_data *data = to_rtk_reset_controller(rcdev); + const struct rtk_reset_desc *desc; + unsigned int mask, val; + + desc = rtk_reset_get_desc(data, idx); + mask = desc->write_en ? (0x3U << desc->bit) : BIT(desc->bit); + val = desc->write_en ? (0x2U << desc->bit) : 0; + + return regmap_update_bits(data->regmap, desc->ofs, mask, val); +} + +static int rtk_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct rtk_reset_data *data = to_rtk_reset_controller(rcdev); + const struct rtk_reset_desc *desc; + unsigned int mask; + + desc = rtk_reset_get_desc(data, idx); + mask = desc->write_en ? (0x3U << desc->bit) : BIT(desc->bit); + + return regmap_set_bits(data->regmap, desc->ofs, mask); +} + +static int rtk_reset_status(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct rtk_reset_data *data = to_rtk_reset_controller(rcdev); + const struct rtk_reset_desc *desc; + unsigned int val; + int ret; + + desc = rtk_reset_get_desc(data, idx); + ret = regmap_read(data->regmap, desc->ofs, &val); + if (ret) + return ret; + + return !((val >> desc->bit) & 1); +} + +const struct reset_control_ops rtk_reset_ops = { + .assert = rtk_reset_assert, + .deassert = rtk_reset_deassert, + .status = rtk_reset_status, +}; +EXPORT_SYMBOL_NS_GPL(rtk_reset_ops, "REALTEK_RESET"); + +MODULE_DESCRIPTION("realtek reset infrastructure"); +MODULE_LICENSE("GPL"); diff --git a/drivers/reset/realtek/reset-rtk-common.h b/drivers/reset/realtek/reset-rtk-common.h new file mode 100644 index 000000000000..3ea35d9573a4 --- /dev/null +++ b/drivers/reset/realtek/reset-rtk-common.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 Realtek Semiconductor Corporation + * Author: Yu-Chun Lin <eleanor.lin@realtek.com> + */ + +#ifndef __RESET_REALTEK_COMMON_H +#define __RESET_REALTEK_COMMON_H + +#include <linux/reset-controller.h> +#include <linux/types.h> + +struct regmap; + +struct rtk_reset_desc { + u32 ofs; + u32 bit; + bool write_en; +}; + +struct rtk_reset_data { + struct reset_controller_dev rcdev; + const struct rtk_reset_desc *descs; + struct regmap *regmap; +}; + +extern const struct reset_control_ops rtk_reset_ops; + +#endif /* __RESET_REALTEK_COMMON_H */ -- 2.43.0 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v16 3/3] reset: realtek: Add RTD1625 reset controller driver 2026-11-12 5:31 [PATCH v16 0/3] reset: realtek: Add RTD1625 reset support Yu-Chun Lin 2026-11-12 5:31 ` [PATCH v16 1/3] dt-bindings: reset: Add Realtek RTD1625 reset IDs Yu-Chun Lin 2026-11-12 5:31 ` [PATCH v16 2/3] reset: Add Realtek basic reset support Yu-Chun Lin @ 2026-11-12 5:31 ` Yu-Chun Lin 2026-11-12 9:41 ` [PATCH v16 0/3] reset: realtek: Add RTD1625 reset support Philipp Zabel 3 siblings, 0 replies; 7+ messages in thread From: Yu-Chun Lin @ 2026-11-12 5:31 UTC (permalink / raw) To: p.zabel, robh, krzk+dt, conor+dt, cylee12 Cc: devicetree, linux-kernel, james.tai, cy.huang, stanley_chang, eleanor.lin From: Cheng-Yu Lee <cylee12@realtek.com> Add support for the CRT (Clock, Reset, and Test) and ISO (Isolation)domain reset controller on the Realtek RTD1625 SoC. The reset controller shares the same register space with the CRT and ISO clock controller. To handle this shared register space, the reset driver is implemented as an auxiliary driver. It will be instantiated and probed via the auxiliary bus by the RTD1625-CRT and RTD1625-ISO clock controller driver. Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com> Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> --- drivers/reset/realtek/Kconfig | 11 ++ drivers/reset/realtek/Makefile | 1 + drivers/reset/realtek/reset-rtd1625.c | 262 ++++++++++++++++++++++++++ 3 files changed, 274 insertions(+) create mode 100644 drivers/reset/realtek/reset-rtd1625.c diff --git a/drivers/reset/realtek/Kconfig b/drivers/reset/realtek/Kconfig index 5ddf8e5c09c7..38591b6a70b3 100644 --- a/drivers/reset/realtek/Kconfig +++ b/drivers/reset/realtek/Kconfig @@ -6,3 +6,14 @@ config RESET_RTK_COMMON Realtek SoCs. It provides shared reset control operations (assert, deassert, status) that other Realtek-specific reset drivers can use. + +config RESET_RTD1625 + tristate "RTD1625 Reset Controller" + depends on ARCH_REALTEK || COMPILE_TEST + select RESET_RTK_COMMON + select AUXILIARY_BUS + help + This enables the reset controller driver for Realtek RTD1625 SoC. + The driver controls reset lines for various peripherals including + PCIe, SATA, HDMI, display, video encoder/decoder, USB, SD, audio, + and other subsystems. diff --git a/drivers/reset/realtek/Makefile b/drivers/reset/realtek/Makefile index 6d68e41748bf..993acd1e2d14 100644 --- a/drivers/reset/realtek/Makefile +++ b/drivers/reset/realtek/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_RESET_RTK_COMMON) += reset-rtk-common.o +obj-$(CONFIG_RESET_RTD1625) += reset-rtd1625.o diff --git a/drivers/reset/realtek/reset-rtd1625.c b/drivers/reset/realtek/reset-rtd1625.c new file mode 100644 index 000000000000..061634e74b5f --- /dev/null +++ b/drivers/reset/realtek/reset-rtd1625.c @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Realtek Semiconductor Corporation + */ + +#include <dt-bindings/reset/realtek,rtd1625.h> +#include <linux/auxiliary_bus.h> +#include <linux/array_size.h> +#include <linux/device.h> +#include <linux/errno.h> +#include <linux/module.h> +#include <linux/slab.h> +#include "reset-rtk-common.h" + +struct rtd1625_reset_info { + const struct rtk_reset_desc *descs; + unsigned int nr_resets; +}; + +static const struct rtk_reset_desc rtd1625_crt_reset_descs[] = { + /* Bank 0: offset 0x0 */ + [RTD1625_CRT_RSTN_MISC] = { .ofs = 0x0, .bit = 0, .write_en = 1 }, + [RTD1625_CRT_RSTN_DIP] = { .ofs = 0x0, .bit = 2, .write_en = 1 }, + [RTD1625_CRT_RSTN_GSPI] = { .ofs = 0x0, .bit = 4, .write_en = 1 }, + [RTD1625_CRT_RSTN_SDS] = { .ofs = 0x0, .bit = 6, .write_en = 1 }, + [RTD1625_CRT_RSTN_SDS_REG] = { .ofs = 0x0, .bit = 8, .write_en = 1 }, + [RTD1625_CRT_RSTN_SDS_PHY] = { .ofs = 0x0, .bit = 10, .write_en = 1 }, + [RTD1625_CRT_RSTN_GPU2D] = { .ofs = 0x0, .bit = 12, .write_en = 1 }, + [RTD1625_CRT_RSTN_DC_PHY] = { .ofs = 0x0, .bit = 22, .write_en = 1 }, + [RTD1625_CRT_RSTN_DCPHY_CRT] = { .ofs = 0x0, .bit = 24, .write_en = 1 }, + [RTD1625_CRT_RSTN_LSADC] = { .ofs = 0x0, .bit = 26, .write_en = 1 }, + [RTD1625_CRT_RSTN_SE] = { .ofs = 0x0, .bit = 28, .write_en = 1 }, + [RTD1625_CRT_RSTN_DLA] = { .ofs = 0x0, .bit = 30, .write_en = 1 }, + /* Bank 1: offset 0x4 */ + [RTD1625_CRT_RSTN_JPEG] = { .ofs = 0x4, .bit = 0, .write_en = 1 }, + [RTD1625_CRT_RSTN_SD] = { .ofs = 0x4, .bit = 2, .write_en = 1 }, + [RTD1625_CRT_RSTN_SDIO] = { .ofs = 0x4, .bit = 6, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCR_CNT] = { .ofs = 0x4, .bit = 8, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE0_STITCH] = { .ofs = 0x4, .bit = 10, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE0_PHY] = { .ofs = 0x4, .bit = 12, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE0] = { .ofs = 0x4, .bit = 14, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE0_CORE] = { .ofs = 0x4, .bit = 16, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE0_POWER] = { .ofs = 0x4, .bit = 18, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE0_NONSTICH] = { .ofs = 0x4, .bit = 20, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE0_PHY_MDIO] = { .ofs = 0x4, .bit = 22, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE0_SGMII_MDIO] = { .ofs = 0x4, .bit = 24, .write_en = 1 }, + [RTD1625_CRT_RSTN_VO2] = { .ofs = 0x4, .bit = 28, .write_en = 1 }, + [RTD1625_CRT_RSTN_MISC_SC0] = { .ofs = 0x4, .bit = 30, .write_en = 1 }, + /* Bank 2: offset 0x8 */ + [RTD1625_CRT_RSTN_MD] = { .ofs = 0x8, .bit = 4, .write_en = 1 }, + [RTD1625_CRT_RSTN_LVDS1] = { .ofs = 0x8, .bit = 6, .write_en = 1 }, + [RTD1625_CRT_RSTN_LVDS2] = { .ofs = 0x8, .bit = 8, .write_en = 1 }, + [RTD1625_CRT_RSTN_MISC_SC1] = { .ofs = 0x8, .bit = 10, .write_en = 1 }, + [RTD1625_CRT_RSTN_I2C_3] = { .ofs = 0x8, .bit = 12, .write_en = 1 }, + [RTD1625_CRT_RSTN_FAN] = { .ofs = 0x8, .bit = 14, .write_en = 1 }, + [RTD1625_CRT_RSTN_TVE] = { .ofs = 0x8, .bit = 16, .write_en = 1 }, + [RTD1625_CRT_RSTN_AIO] = { .ofs = 0x8, .bit = 18, .write_en = 1 }, + [RTD1625_CRT_RSTN_VO] = { .ofs = 0x8, .bit = 20, .write_en = 1 }, + [RTD1625_CRT_RSTN_MIPI_CSI] = { .ofs = 0x8, .bit = 22, .write_en = 1 }, + [RTD1625_CRT_RSTN_HDMIRX] = { .ofs = 0x8, .bit = 24, .write_en = 1 }, + [RTD1625_CRT_RSTN_HDMIRX_WRAP] = { .ofs = 0x8, .bit = 26, .write_en = 1 }, + [RTD1625_CRT_RSTN_HDMI] = { .ofs = 0x8, .bit = 28, .write_en = 1 }, + [RTD1625_CRT_RSTN_DISP] = { .ofs = 0x8, .bit = 30, .write_en = 1 }, + /* Bank 3: offset 0xc */ + [RTD1625_CRT_RSTN_SATA_PHY_POW1] = { .ofs = 0xc, .bit = 0, .write_en = 1 }, + [RTD1625_CRT_RSTN_SATA_PHY_POW0] = { .ofs = 0xc, .bit = 2, .write_en = 1 }, + [RTD1625_CRT_RSTN_SATA_MDIO1] = { .ofs = 0xc, .bit = 4, .write_en = 1 }, + [RTD1625_CRT_RSTN_SATA_MDIO0] = { .ofs = 0xc, .bit = 6, .write_en = 1 }, + [RTD1625_CRT_RSTN_SATA_WRAP] = { .ofs = 0xc, .bit = 8, .write_en = 1 }, + [RTD1625_CRT_RSTN_SATA_MAC_P1] = { .ofs = 0xc, .bit = 10, .write_en = 1 }, + [RTD1625_CRT_RSTN_SATA_MAC_P0] = { .ofs = 0xc, .bit = 12, .write_en = 1 }, + [RTD1625_CRT_RSTN_SATA_MAC_COM] = { .ofs = 0xc, .bit = 14, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE1_STITCH] = { .ofs = 0xc, .bit = 16, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE1_PHY] = { .ofs = 0xc, .bit = 18, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE1] = { .ofs = 0xc, .bit = 20, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE1_CORE] = { .ofs = 0xc, .bit = 22, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE1_POWER] = { .ofs = 0xc, .bit = 24, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE1_NONSTICH] = { .ofs = 0xc, .bit = 26, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE1_PHY_MDIO] = { .ofs = 0xc, .bit = 28, .write_en = 1 }, + [RTD1625_CRT_RSTN_HDMITOP] = { .ofs = 0xc, .bit = 30, .write_en = 1 }, + /* Bank 4: offset 0x68 */ + [RTD1625_CRT_RSTN_I2C_4] = { .ofs = 0x68, .bit = 2, .write_en = 1 }, + [RTD1625_CRT_RSTN_I2C_5] = { .ofs = 0x68, .bit = 4, .write_en = 1 }, + [RTD1625_CRT_RSTN_TSIO] = { .ofs = 0x68, .bit = 6, .write_en = 1 }, + [RTD1625_CRT_RSTN_VI] = { .ofs = 0x68, .bit = 8, .write_en = 1 }, + [RTD1625_CRT_RSTN_EDP] = { .ofs = 0x68, .bit = 10, .write_en = 1 }, + [RTD1625_CRT_RSTN_VE1_MMU] = { .ofs = 0x68, .bit = 12, .write_en = 1 }, + [RTD1625_CRT_RSTN_VE1_MMU_FUNC] = { .ofs = 0x68, .bit = 14, .write_en = 1 }, + [RTD1625_CRT_RSTN_HSE_MMU] = { .ofs = 0x68, .bit = 16, .write_en = 1 }, + [RTD1625_CRT_RSTN_HSE_MMU_FUNC] = { .ofs = 0x68, .bit = 18, .write_en = 1 }, + [RTD1625_CRT_RSTN_MDLM2M] = { .ofs = 0x68, .bit = 20, .write_en = 1 }, + [RTD1625_CRT_RSTN_ISO_GSPI] = { .ofs = 0x68, .bit = 22, .write_en = 1 }, + [RTD1625_CRT_RSTN_SOFT_NPU] = { .ofs = 0x68, .bit = 24, .write_en = 1 }, + [RTD1625_CRT_RSTN_SPI2EMMC] = { .ofs = 0x68, .bit = 26, .write_en = 1 }, + [RTD1625_CRT_RSTN_EARC] = { .ofs = 0x68, .bit = 28, .write_en = 1 }, + [RTD1625_CRT_RSTN_VE1] = { .ofs = 0x68, .bit = 30, .write_en = 1 }, + /* Bank 5: offset 0x90 */ + [RTD1625_CRT_RSTN_PCIE2_STITCH] = { .ofs = 0x90, .bit = 0, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE2_PHY] = { .ofs = 0x90, .bit = 2, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE2] = { .ofs = 0x90, .bit = 4, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE2_CORE] = { .ofs = 0x90, .bit = 6, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE2_POWER] = { .ofs = 0x90, .bit = 8, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE2_NONSTICH] = { .ofs = 0x90, .bit = 10, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE2_PHY_MDIO] = { .ofs = 0x90, .bit = 12, .write_en = 1 }, + [RTD1625_CRT_RSTN_DCPHY_UMCTL2] = { .ofs = 0x90, .bit = 14, .write_en = 1 }, + [RTD1625_CRT_RSTN_MIPI_DSI] = { .ofs = 0x90, .bit = 16, .write_en = 1 }, + [RTD1625_CRT_RSTN_HIFM] = { .ofs = 0x90, .bit = 18, .write_en = 1 }, + [RTD1625_CRT_RSTN_NSRAM] = { .ofs = 0x90, .bit = 20, .write_en = 1 }, + [RTD1625_CRT_RSTN_AUCPU0_REG] = { .ofs = 0x90, .bit = 22, .write_en = 1 }, + [RTD1625_CRT_RSTN_MDL_GENPW] = { .ofs = 0x90, .bit = 24, .write_en = 1 }, + [RTD1625_CRT_RSTN_MDL_CHIP] = { .ofs = 0x90, .bit = 26, .write_en = 1 }, + [RTD1625_CRT_RSTN_MDL_IP] = { .ofs = 0x90, .bit = 28, .write_en = 1 }, + [RTD1625_CRT_RSTN_TEST_MUX] = { .ofs = 0x90, .bit = 30, .write_en = 1 }, + /* Bank 6: offset 0xb8 */ + [RTD1625_CRT_RSTN_ISO_BIST] = { .ofs = 0xb8, .bit = 0, .write_en = 1 }, + [RTD1625_CRT_RSTN_MAIN_BIST] = { .ofs = 0xb8, .bit = 2, .write_en = 1 }, + [RTD1625_CRT_RSTN_MAIN2_BIST] = { .ofs = 0xb8, .bit = 4, .write_en = 1 }, + [RTD1625_CRT_RSTN_VE1_BIST] = { .ofs = 0xb8, .bit = 6, .write_en = 1 }, + [RTD1625_CRT_RSTN_VE2_BIST] = { .ofs = 0xb8, .bit = 8, .write_en = 1 }, + [RTD1625_CRT_RSTN_DCPHY_BIST] = { .ofs = 0xb8, .bit = 10, .write_en = 1 }, + [RTD1625_CRT_RSTN_GPU_BIST] = { .ofs = 0xb8, .bit = 12, .write_en = 1 }, + [RTD1625_CRT_RSTN_DISP_BIST] = { .ofs = 0xb8, .bit = 14, .write_en = 1 }, + [RTD1625_CRT_RSTN_NPU_BIST] = { .ofs = 0xb8, .bit = 16, .write_en = 1 }, + [RTD1625_CRT_RSTN_CAS_BIST] = { .ofs = 0xb8, .bit = 18, .write_en = 1 }, + [RTD1625_CRT_RSTN_VE4_BIST] = { .ofs = 0xb8, .bit = 20, .write_en = 1 }, + /* Bank 7: offset 0x454 (DUMMY0, no write_en) */ + [RTD1625_CRT_RSTN_EMMC] = { .ofs = 0x454, .bit = 0 }, + /* Bank 8: offset 0x458 (DUMMY1, no write_en) */ + [RTD1625_CRT_RSTN_GPU] = { .ofs = 0x458, .bit = 0 }, + /* Bank 9: offset 0x464 (DUMMY4, no write_en) */ + [RTD1625_CRT_RSTN_VE2] = { .ofs = 0x464, .bit = 0 }, + /* Bank 10: offset 0x880 */ + [RTD1625_CRT_RSTN_UR1] = { .ofs = 0x880, .bit = 0, .write_en = 1 }, + [RTD1625_CRT_RSTN_UR2] = { .ofs = 0x880, .bit = 2, .write_en = 1 }, + [RTD1625_CRT_RSTN_UR3] = { .ofs = 0x880, .bit = 4, .write_en = 1 }, + [RTD1625_CRT_RSTN_UR4] = { .ofs = 0x880, .bit = 6, .write_en = 1 }, + [RTD1625_CRT_RSTN_UR5] = { .ofs = 0x880, .bit = 8, .write_en = 1 }, + [RTD1625_CRT_RSTN_UR6] = { .ofs = 0x880, .bit = 10, .write_en = 1 }, + [RTD1625_CRT_RSTN_UR7] = { .ofs = 0x880, .bit = 12, .write_en = 1 }, + [RTD1625_CRT_RSTN_UR8] = { .ofs = 0x880, .bit = 14, .write_en = 1 }, + [RTD1625_CRT_RSTN_UR9] = { .ofs = 0x880, .bit = 16, .write_en = 1 }, + [RTD1625_CRT_RSTN_UR_TOP] = { .ofs = 0x880, .bit = 18, .write_en = 1 }, + [RTD1625_CRT_RSTN_I2C_7] = { .ofs = 0x880, .bit = 28, .write_en = 1 }, + [RTD1625_CRT_RSTN_I2C_6] = { .ofs = 0x880, .bit = 30, .write_en = 1 }, + /* Bank 11: offset 0x890 */ + [RTD1625_CRT_RSTN_SPI0] = { .ofs = 0x890, .bit = 0, .write_en = 1 }, + [RTD1625_CRT_RSTN_SPI1] = { .ofs = 0x890, .bit = 2, .write_en = 1 }, + [RTD1625_CRT_RSTN_SPI2] = { .ofs = 0x890, .bit = 4, .write_en = 1 }, + [RTD1625_CRT_RSTN_LSADC0] = { .ofs = 0x890, .bit = 16, .write_en = 1 }, + [RTD1625_CRT_RSTN_LSADC1] = { .ofs = 0x890, .bit = 18, .write_en = 1 }, + [RTD1625_CRT_RSTN_ISOMIS_DMA] = { .ofs = 0x890, .bit = 20, .write_en = 1 }, + [RTD1625_CRT_RSTN_AUDIO_ADC] = { .ofs = 0x890, .bit = 22, .write_en = 1 }, + [RTD1625_CRT_RSTN_DPTX] = { .ofs = 0x890, .bit = 24, .write_en = 1 }, + [RTD1625_CRT_RSTN_AUCPU1_REG] = { .ofs = 0x890, .bit = 26, .write_en = 1 }, + [RTD1625_CRT_RSTN_EDPTX] = { .ofs = 0x890, .bit = 28, .write_en = 1 }, +}; + +static const struct rtd1625_reset_info rtd1625_crt_info = { + .descs = rtd1625_crt_reset_descs, + .nr_resets = ARRAY_SIZE(rtd1625_crt_reset_descs), +}; + +static const struct rtk_reset_desc rtd1625_iso_reset_descs[] = { + [RTD1625_ISO_RSTN_VFD] = { .ofs = 0x88, .bit = 0 }, + [RTD1625_ISO_RSTN_CEC0] = { .ofs = 0x88, .bit = 2 }, + [RTD1625_ISO_RSTN_CEC1] = { .ofs = 0x88, .bit = 3 }, + [RTD1625_ISO_RSTN_CBUSTX] = { .ofs = 0x88, .bit = 5 }, + [RTD1625_ISO_RSTN_CBUSRX] = { .ofs = 0x88, .bit = 6 }, + [RTD1625_ISO_RSTN_USB3_PHY2_XTAL_POW] = { .ofs = 0x88, .bit = 7 }, + [RTD1625_ISO_RSTN_UR0] = { .ofs = 0x88, .bit = 8 }, + [RTD1625_ISO_RSTN_GMAC] = { .ofs = 0x88, .bit = 9 }, + [RTD1625_ISO_RSTN_GPHY] = { .ofs = 0x88, .bit = 10 }, + [RTD1625_ISO_RSTN_I2C_0] = { .ofs = 0x88, .bit = 11 }, + [RTD1625_ISO_RSTN_I2C_1] = { .ofs = 0x88, .bit = 12 }, + [RTD1625_ISO_RSTN_CBUS] = { .ofs = 0x88, .bit = 13 }, + [RTD1625_ISO_RSTN_USB_DRD] = { .ofs = 0x88, .bit = 14 }, + [RTD1625_ISO_RSTN_USB_HOST] = { .ofs = 0x88, .bit = 15 }, + [RTD1625_ISO_RSTN_USB_PHY_0] = { .ofs = 0x88, .bit = 16 }, + [RTD1625_ISO_RSTN_USB_PHY_1] = { .ofs = 0x88, .bit = 17 }, + [RTD1625_ISO_RSTN_USB_PHY_2] = { .ofs = 0x88, .bit = 18 }, + [RTD1625_ISO_RSTN_USB] = { .ofs = 0x88, .bit = 19 }, + [RTD1625_ISO_RSTN_TYPE_C] = { .ofs = 0x88, .bit = 20 }, + [RTD1625_ISO_RSTN_USB_U3_HOST] = { .ofs = 0x88, .bit = 21 }, + [RTD1625_ISO_RSTN_USB3_PHY0_POW] = { .ofs = 0x88, .bit = 22 }, + [RTD1625_ISO_RSTN_USB3_P0_MDIO] = { .ofs = 0x88, .bit = 23 }, + [RTD1625_ISO_RSTN_USB3_PHY1_POW] = { .ofs = 0x88, .bit = 24 }, + [RTD1625_ISO_RSTN_USB3_P1_MDIO] = { .ofs = 0x88, .bit = 25 }, + [RTD1625_ISO_RSTN_VTC] = { .ofs = 0x88, .bit = 26 }, + [RTD1625_ISO_RSTN_USB3_PHY2_POW] = { .ofs = 0x88, .bit = 27 }, + [RTD1625_ISO_RSTN_USB3_P2_MDIO] = { .ofs = 0x88, .bit = 28 }, + [RTD1625_ISO_RSTN_USB_PHY_3] = { .ofs = 0x88, .bit = 29 }, + [RTD1625_ISO_RSTN_USB_PHY_4] = { .ofs = 0x88, .bit = 30 }, +}; + +static const struct rtd1625_reset_info rtd1625_iso_info = { + .descs = rtd1625_iso_reset_descs, + .nr_resets = ARRAY_SIZE(rtd1625_iso_reset_descs), +}; + +static const struct rtk_reset_desc rtd1625_iso_s_reset_descs[] = { + [RTD1625_ISO_S_RSTN_ISOM_MIS] = { .ofs = 0x310, .bit = 0, .write_en = 1 }, + [RTD1625_ISO_S_RSTN_GPIOM] = { .ofs = 0x310, .bit = 2, .write_en = 1 }, + [RTD1625_ISO_S_RSTN_TIMER7] = { .ofs = 0x310, .bit = 4, .write_en = 1 }, + [RTD1625_ISO_S_RSTN_IRDA] = { .ofs = 0x310, .bit = 6, .write_en = 1 }, + [RTD1625_ISO_S_RSTN_UR10] = { .ofs = 0x310, .bit = 8, .write_en = 1 }, +}; + +static const struct rtd1625_reset_info rtd1625_iso_s_info = { + .descs = rtd1625_iso_s_reset_descs, + .nr_resets = ARRAY_SIZE(rtd1625_iso_s_reset_descs), +}; + +static int rtd1625_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + const struct rtd1625_reset_info *info; + struct device *dev = &adev->dev; + struct rtk_reset_data *data; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + info = (const struct rtd1625_reset_info *)id->driver_data; + + data->descs = info->descs; + data->regmap = dev_get_platdata(dev); + data->rcdev.owner = THIS_MODULE; + data->rcdev.nr_resets = info->nr_resets; + data->rcdev.ops = &rtk_reset_ops; + data->rcdev.dev = dev; + data->rcdev.of_node = dev->of_node; + + return devm_reset_controller_register(dev, &data->rcdev); +} + +static const struct auxiliary_device_id rtd1625_reset_ids[] = { + { + .name = "clk_rtk.rtd1625_crt_rst", + .driver_data = (kernel_ulong_t)&rtd1625_crt_info }, + { + .name = "clk_rtk.rtd1625_iso_rst", + .driver_data = (kernel_ulong_t)&rtd1625_iso_info }, + { + .name = "clk_rtk.rtd1625_iso_s_rst", + .driver_data = (kernel_ulong_t)&rtd1625_iso_s_info }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(auxiliary, rtd1625_reset_ids); + +static struct auxiliary_driver rtd1625_reset_driver = { + .probe = rtd1625_reset_probe, + .id_table = rtd1625_reset_ids, + .driver = { + .name = "rtd1625-reset", + }, +}; +module_auxiliary_driver(rtd1625_reset_driver); + +MODULE_DESCRIPTION("Realtek RTD1625 Reset Controller Driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("REALTEK_RESET"); -- 2.43.0 ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v16 0/3] reset: realtek: Add RTD1625 reset support 2026-11-12 5:31 [PATCH v16 0/3] reset: realtek: Add RTD1625 reset support Yu-Chun Lin ` (2 preceding siblings ...) 2026-11-12 5:31 ` [PATCH v16 3/3] reset: realtek: Add RTD1625 reset controller driver Yu-Chun Lin @ 2026-11-12 9:41 ` Philipp Zabel 3 siblings, 0 replies; 7+ messages in thread From: Philipp Zabel @ 2026-11-12 9:41 UTC (permalink / raw) To: Yu-Chun Lin, robh, krzk+dt, conor+dt, cylee12 Cc: devicetree, linux-kernel, james.tai, cy.huang, stanley_chang On Do, 2026-11-12 at 13:31 +0800, Yu-Chun Lin wrote: > Hi all, > > This series adds reset controller support for the Realtek RTD1625 SoC. > > Since the reset and clock controllers share the same register space, they > are now decoupled via the Auxiliary Bus framework. This allows the reset > drivers to be submitted as a separate series. > > [...] Applied to reset/next, thanks! [1/3] dt-bindings: reset: Add Realtek RTD1625 reset IDs https://git.kernel.org/pub/scm/linux/kernel/git/pza/linux.git/commit/?id=3b8e9b3eebd5 [2/3] reset: Add Realtek basic reset support https://git.kernel.org/pub/scm/linux/kernel/git/pza/linux.git/commit/?id=9d125752e1a1 [3/3] reset: realtek: Add RTD1625 reset controller driver https://git.kernel.org/pub/scm/linux/kernel/git/pza/linux.git/commit/?id=2716aec8c63a regards Philipp ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2026-11-12 9:41 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2026-11-12 5:31 [PATCH v16 0/3] reset: realtek: Add RTD1625 reset support Yu-Chun Lin 2026-11-12 5:31 ` [PATCH v16 1/3] dt-bindings: reset: Add Realtek RTD1625 reset IDs Yu-Chun Lin 2026-11-12 9:08 ` Krzysztof Kozlowski 2026-11-12 9:10 ` Krzysztof Kozlowski 2026-11-12 5:31 ` [PATCH v16 2/3] reset: Add Realtek basic reset support Yu-Chun Lin 2026-11-12 5:31 ` [PATCH v16 3/3] reset: realtek: Add RTD1625 reset controller driver Yu-Chun Lin 2026-11-12 9:41 ` [PATCH v16 0/3] reset: realtek: Add RTD1625 reset support Philipp Zabel
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®