From: "Benjamin Herrenschmidt" <benh@kernel.crashing.org>
To: "Justin T. Gibbs" <gibbs@scsiguy.com>,
"Marcelo Tosatti" <marcelo@conectiva.com.br>
Cc: lkml <linux-kernel@vger.kernel.org>
Subject: Re: 2.4.20pre7, aic7xxx-6.2.8: Panic: HOST_MSG_LOOP with invalid SCB 0
Date: Mon, 23 Sep 2002 09:15:42 +0200 [thread overview]
Message-ID: <20020923071542.32214@192.168.4.1> (raw)
In-Reply-To: <2632550816.1032817396@aslan.btc.adaptec.com>
>No, it is not write posting. It is usually a problem with write
>combining/merging and or read prefetch on devices that do not
>support this feature. The memory BAR on the aic7xxx chips does
>not have the PREFETCH bit set so these types of operations are
>forbidden by the spec. The end result are missed writes and
>state read data leading to all kinds of driver confusion.
>
>Often these issues are really register layout dependent. If
>you never have to access two registers that are right next to
>each other, the chipset can't write combine, etc.
Ok, well. Indeed, adding a read on all writes may help here.
Does this affect the performances significantly ?
Ben.
prev parent reply other threads:[~2002-09-24 7:34 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-09-20 5:28 Ville Herva
2002-09-20 15:37 ` Justin T. Gibbs
2002-09-20 18:19 ` 2.4.19, 2.4.20pre7, problem with aic7xxx driver Stephan von Krawczynski
2002-09-20 19:48 ` Phil Brutsche
2002-09-20 19:56 ` Stephan von Krawczynski
2002-09-23 15:28 ` 2.4.20pre7, aic7xxx-6.2.8: Panic: HOST_MSG_LOOP with invalid SCB 0 Marcelo Tosatti
2002-09-23 17:35 ` Justin T. Gibbs
2002-09-23 16:54 ` Marcelo Tosatti
2002-09-23 6:35 ` Benjamin Herrenschmidt
2002-09-23 21:43 ` Justin T. Gibbs
2002-09-23 7:15 ` Benjamin Herrenschmidt [this message]
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