Re: [BKPATCH] allow pci primary peer busses to have parents

[James Bottomley <James.Bottomley@steeleye.com>]

On Wed, Dec 04, 2002 at 11:18:24AM -0600, James Bottomley wrote:
> Now that the generic device model allows a coherent bus tree to be built

ink@jurassic.park.msu.ru said:
> Unfortunately it doesn't.

OK, consider the phrase for architectures with subordinate PCI busses added.

ink@jurassic.park.msu.ru said:
>  Currently those legacy, PnP, EISA devices all have virtual parents,
> which has nothing to do with reality. Modern systems (including most
> PCs) hang these buses off PCI bus using PCI-to-{E}ISA bridge. Such
> systems must be able to register these buses upon discovery of the ISA
> bridges (from pci layer), and use them as a parent device for legacy/
> isa/pnp stuff. This will be absolutely required if DMA operations are
> moved from pci_dev to the generic device. 

Well, we are moving in this direction.  I've already done the conversion for 
MCA.  Marc Zyngier has done it for EISA.  I believe someone is looking at PnP 
ISA.  ISA, as a non-probe'able bus fits into the legacy bus scheme anyway.

> The `sysdata' arg already contains info about parent host-to-pci
> controller on many platforms. I don't think that we need to duplicate
> it with another one. I was thinking about something like this instead
> of `sysdata': 

That's PCI specific.  We need a coherent tree in the generic model.  To do 
this, the PCI parent information has to be available just using the struct 
device, without having to cast it to pci_dev and look at pci specific fields.

This is a simplification requirement for machines whose IOMMUs lie on other 
bus types above the PCI busses.  You have to be able to walk up the device 
tree until you find the IOMMU.  Since you're sharing the implementation with 
the non-PCI busses, you need to be able to do this in a generic manner.

James