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* [PATCH] 2.6 PPC64 Power5 PCI boot fixes
@ 2004-07-02 19:29 linas
  2004-07-02 19:32 ` linas
  0 siblings, 1 reply; 2+ messages in thread
From: linas @ 2004-07-02 19:29 UTC (permalink / raw)
  To: paulus, paulus; +Cc: linuxppc64-dev, linux-kernel



Paul,

Please review and forward upstream the following PCI EEH patch.

This patch allows ppc64 to boot on the Power5 architecture.  The 
new Power5 PCI bridge design requires EEH to be enabled for all PCI
devices, not just some PCI devices.  In addition, this patch moves
the check for PCI to ISA bridges out of perf critical code, and into
initialization code.   This also avoids race conditions where the 
device type might not have been set.  Also, some whitespace fixes, 
and some error-message-printing beautification. 

Signed-off-by: Linas Vepstas <linas@linas.org>

--linas

^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH] 2.6 PPC64 Power5 PCI boot fixes
  2004-07-02 19:29 [PATCH] 2.6 PPC64 Power5 PCI boot fixes linas
@ 2004-07-02 19:32 ` linas
  0 siblings, 0 replies; 2+ messages in thread
From: linas @ 2004-07-02 19:32 UTC (permalink / raw)
  To: paulus, paulus; +Cc: linuxppc64-dev, linux-kernel

[-- Attachment #1: Type: text/plain, Size: 738 bytes --]

Resending, I forgot to attach the patch last time.

On Fri, Jul 02, 2004 at 02:29:06PM -0500, linas@austin.ibm.com wrote:
> 
> Paul,
> 
> Please review and forward upstream the following PCI EEH patch.
> 
> This patch allows ppc64 to boot on the Power5 architecture.  The 
> new Power5 PCI bridge design requires EEH to be enabled for all PCI
> devices, not just some PCI devices.  In addition, this patch moves
> the check for PCI to ISA bridges out of perf critical code, and into
> initialization code.   This also avoids race conditions where the 
> device type might not have been set.  Also, some whitespace fixes, 
> and some error-message-printing beautification. 
> 
> Signed-off-by: Linas Vepstas <linas@linas.org>
> 
> --linas

[-- Attachment #2: eeh-isa-power5.patch --]
[-- Type: text/plain, Size: 3724 bytes --]

===== arch/ppc64/kernel/eeh.c 1.21 vs edited =====
--- 1.21/arch/ppc64/kernel/eeh.c	Fri Jul  2 13:49:21 2004
+++ edited/arch/ppc64/kernel/eeh.c	Fri Jul  2 14:06:51 2004
@@ -394,12 +394,6 @@
 		return val;
 	}
 
-        /* Make sure we aren't ISA */
-        if (!strcmp(dn->type, "isa")) {
-                pci_dev_put(dev);
-                return val;
-        }
-
 	if (!dn->eeh_config_addr) {
 		pci_dev_put(dev);
 		return val;
@@ -462,6 +456,7 @@
 struct eeh_early_enable_info {
 	unsigned int buid_hi;
 	unsigned int buid_lo;
+	int force_off;
 };
 
 /* Enable eeh for the given device node. */
@@ -476,6 +471,8 @@
 	u32 *regs;
 	int enable;
 
+	dn->eeh_mode = 0;
+
 	if (status && strcmp(status, "ok") != 0)
 		return NULL;	/* ignore devices with bad status */
 
@@ -489,6 +486,12 @@
 	     *device_id == 0x0188 || *device_id == 0x0302))
 		return NULL;
 
+	/* There is nothing to check on PCI to ISA bridges */
+	if (dn->type && !strcmp(dn->type, "isa")) {
+		dn->eeh_mode |= EEH_MODE_NOCHECK;
+		return NULL;
+	}
+
 	/*
 	 * Now decide if we are going to "Disable" EEH checking
 	 * for this device.  We still run with the EEH hardware active,
@@ -505,12 +508,12 @@
 				   enable)) {
 		if (enable) {
 			printk(KERN_WARNING "EEH: %s user requested to run "
-			       "without EEH.\n", dn->full_name);
+			       "without EEH checking.\n", dn->full_name);
 			enable = 0;
 		}
 	}
 
-	if (!enable) {
+	if (!enable || info->force_off) {
 		dn->eeh_mode = EEH_MODE_NOCHECK;
 		return NULL;
 	}
@@ -540,8 +543,8 @@
 			       dn->full_name);
 #endif
 		} else {
-			printk(KERN_WARNING "EEH: %s: could not enable EEH, rtas_call failed.\n",
-			       dn->full_name);
+			printk(KERN_WARNING "EEH: %s: could not enable EEH, rtas_call failed; rc=%d\n",
+			       dn->full_name, ret);
 		}
 	} else {
 		printk(KERN_WARNING "EEH: %s: unable to get reg property.\n",
@@ -567,10 +570,18 @@
  */
 void __init eeh_init(void)
 {
-	struct device_node *phb;
+	struct device_node *phb, *np;
 	struct eeh_early_enable_info info;
 	char *eeh_force_off = strstr(saved_command_line, "eeh-force-off");
 
+	init_pci_config_tokens();
+
+	np = of_find_node_by_path("/rtas");
+	if (np == NULL) {
+		printk(KERN_WARNING "EEH: RTAS not found !\n");
+		return;
+	}
+
 	ibm_set_eeh_option = rtas_token("ibm,set-eeh-option");
 	ibm_set_slot_reset = rtas_token("ibm,set-slot-reset");
 	ibm_read_slot_reset_state = rtas_token("ibm,read-slot-reset-state");
@@ -578,14 +589,14 @@
 	if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE)
 		return;
 
+	info.force_off = 0;
 	if (eeh_force_off) {
 		printk(KERN_WARNING "EEH: WARNING: PCI Enhanced I/O Error "
 		       "Handling is user disabled\n");
-		return;
+		info.force_off = 1;
 	}
 
 	/* Enable EEH for all adapters.  Note that eeh requires buid's */
-	init_pci_config_tokens();
 	for (phb = of_find_node_by_name(NULL, "pci"); phb;
 	     phb = of_find_node_by_name(phb, "pci")) {
 		unsigned long buid;
@@ -599,8 +610,11 @@
 		traverse_pci_devices(phb, early_enable_eeh, NULL, &info);
 	}
 
-	if (eeh_subsystem_enabled)
+	if (eeh_subsystem_enabled) {
 		printk(KERN_INFO "EEH: PCI Enhanced I/O Error Handling Enabled\n");
+	} else {
+		printk(KERN_WARNING "EEH: disabled PCI Enhanced I/O Error Handling\n");
+	}
 }
 
 /**
@@ -740,10 +754,10 @@
 }
 
 static struct file_operations proc_eeh_operations = {
-	.open		= proc_eeh_open,
-	.read		= seq_read,
-	.llseek		= seq_lseek,
-	.release	= single_release,
+	.open      = proc_eeh_open,
+	.read      = seq_read,
+	.llseek    = seq_lseek,
+	.release   = single_release,
 };
 
 static int __init eeh_init_proc(void)
@@ -756,7 +770,7 @@
 			e->proc_fops = &proc_eeh_operations;
 	}
 
-        return 0;
+	return 0;
 }
 __initcall(eeh_init_proc);
 

^ permalink raw reply	[flat|nested] 2+ messages in thread

end of thread, other threads:[~2004-07-02 19:33 UTC | newest]

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2004-07-02 19:29 [PATCH] 2.6 PPC64 Power5 PCI boot fixes linas
2004-07-02 19:32 ` linas

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