* [patch 062/198] ahci: AHCI mode SATA patch for Intel ESB2
@ 2005-04-12 10:31 akpm
2005-04-12 18:32 ` Jeff Garzik
0 siblings, 1 reply; 2+ messages in thread
From: akpm @ 2005-04-12 10:31 UTC (permalink / raw)
To: torvalds; +Cc: linux-kernel, akpm, jason.d.gaston, Jason.d.gaston, linux-scsi
From: Jason Gaston <jason.d.gaston@intel.com>
This patch adds the Intel ESB2 DID's to the ahci.c file for AHCI mode SATA
support.
Signed-off-by: Jason Gaston <Jason.d.gaston@intel.com>
Cc: <linux-scsi@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
---
25-akpm/drivers/scsi/ahci.c | 6 ++++++
1 files changed, 6 insertions(+)
diff -puN drivers/scsi/ahci.c~ahci-ahci-mode-sata-patch-for-intel-esb2 drivers/scsi/ahci.c
--- 25/drivers/scsi/ahci.c~ahci-ahci-mode-sata-patch-for-intel-esb2 2005-04-12 03:21:18.132380360 -0700
+++ 25-akpm/drivers/scsi/ahci.c 2005-04-12 03:21:18.135379904 -0700
@@ -257,6 +257,12 @@ static struct pci_device_id ahci_pci_tbl
board_ahci }, /* ICH7R */
{ PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
board_ahci }, /* ULi M5288 */
+ { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ board_ahci }, /* ESB2 */
+ { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ board_ahci }, /* ESB2 */
+ { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ board_ahci }, /* ESB2 */
{ } /* terminate list */
};
_
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [patch 062/198] ahci: AHCI mode SATA patch for Intel ESB2
2005-04-12 10:31 [patch 062/198] ahci: AHCI mode SATA patch for Intel ESB2 akpm
@ 2005-04-12 18:32 ` Jeff Garzik
0 siblings, 0 replies; 2+ messages in thread
From: Jeff Garzik @ 2005-04-12 18:32 UTC (permalink / raw)
To: akpm; +Cc: torvalds, linux-kernel, jason.d.gaston, linux-scsi
On Tue, Apr 12, 2005 at 03:31:34AM -0700, akpm@osdl.org wrote:
>
> From: Jason Gaston <jason.d.gaston@intel.com>
>
> This patch adds the Intel ESB2 DID's to the ahci.c file for AHCI mode SATA
> support.
Please don't send libata stuff directly to Linus.
Even a patch that appears as simple as this has complications:
The Intel ICH7 combined mode still needs sorting out; combined mode and
another BIOS option (IDE/AHCI) can change the PCI IDs that the
southbridge exports.
I don't want to commit support for -half- the configurations, which
oh-by-the-way will fail if even those users tweak the BIOS options.
Jeff
^ permalink raw reply [flat|nested] 2+ messages in thread
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