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From: Andrew Morton <akpm@osdl.org>
To: Andi Kleen <ak@suse.de>
Cc: hugh@veritas.com, luming.yu@intel.com, racing.guo@intel.com,
	ak@suse.de, davej@redhat.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH -mm] x86 port lockless MCE quirky bank0
Date: Tue, 17 May 2005 15:39:41 -0700	[thread overview]
Message-ID: <20050517153941.7d99d1f6.akpm@osdl.org> (raw)
In-Reply-To: <20050517202428.GD307@wotan.suse.de>

Andi Kleen <ak@suse.de> wrote:
>
> > +	if ((c->x86_vendor == X86_VENDOR_AMD ||
> > +	     c->x86_vendor == X86_VENDOR_INTEL) && c->x86 == 6) {
> > +		/*
> > +		 * Intel P6 cores go bang quickly when bank0 is enabled.
> > +	 	 * Some Athlons cause spurious MCEs when bank0 is enabled.
> > +		 */
> > +		quirky_bank0 = 1;
> > +	}
> 
> That's wrong on K8 AMD machines at least. You need to check c->x86
> there too.
> 
> And better would be to just do bank[0] = 0 instead of
> adding the new variable.
> 
> -Andi
> 
> P.S.: Also Yu Luming can you please submit an updated patch that keeps mce.c
> in arch/x86_64 like we discussed earlier?

Yes.  I'll drop the following from -mm:

x86-port-lockless-mce-preparation.patch
x86-port-lockless-mce-implementation.patch
x86-port-lockless-mce-implementation-fix.patch
x86-port-lockless-mce-implementation-fix-2.patch


  reply	other threads:[~2005-05-17 22:51 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2005-05-17 20:18 Hugh Dickins
2005-05-17 20:24 ` Andi Kleen
2005-05-17 22:39   ` Andrew Morton [this message]
2005-05-18 12:34     ` Hugh Dickins

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