From: Andi Kleen <ak@suse.de>
To: Hugh Dickins <hugh@veritas.com>
Cc: Andrew Morton <akpm@osdl.org>, "Yu, Luming" <luming.yu@intel.com>,
"Guo, Racing" <racing.guo@intel.com>, Andi Kleen <ak@suse.de>,
Dave Jones <davej@redhat.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH -mm] x86 port lockless MCE quirky bank0
Date: Tue, 17 May 2005 22:24:28 +0200 [thread overview]
Message-ID: <20050517202428.GD307@wotan.suse.de> (raw)
In-Reply-To: <Pine.LNX.4.61.0505172107490.5585@goblin.wat.veritas.com>
> + if ((c->x86_vendor == X86_VENDOR_AMD ||
> + c->x86_vendor == X86_VENDOR_INTEL) && c->x86 == 6) {
> + /*
> + * Intel P6 cores go bang quickly when bank0 is enabled.
> + * Some Athlons cause spurious MCEs when bank0 is enabled.
> + */
> + quirky_bank0 = 1;
> + }
That's wrong on K8 AMD machines at least. You need to check c->x86
there too.
And better would be to just do bank[0] = 0 instead of
adding the new variable.
-Andi
P.S.: Also Yu Luming can you please submit an updated patch that keeps mce.c
in arch/x86_64 like we discussed earlier?
next prev parent reply other threads:[~2005-05-17 20:24 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-05-17 20:18 Hugh Dickins
2005-05-17 20:24 ` Andi Kleen [this message]
2005-05-17 22:39 ` Andrew Morton
2005-05-18 12:34 ` Hugh Dickins
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