From: Ingo Molnar <mingo@elte.hu>
To: Karsten Wiese <annabellesgarden@yahoo.de>
Cc: linux-kernel@vger.kernel.org, discuss@x86-64.org, ak@suse.de
Subject: Re: [RFC] AMD64 @ K8T800/VT8237: Doubled IOAPIC-level-interrupt rate
Date: Thu, 4 Aug 2005 17:19:11 +0200 [thread overview]
Message-ID: <20050804151911.GA20765@elte.hu> (raw)
In-Reply-To: <200508041625.41296.annabellesgarden@yahoo.de>
* Karsten Wiese <annabellesgarden@yahoo.de> wrote:
> Hi,
>
> this should likely be addressed to VIA Taiwan,
> but I don't know their engineer's e-mail address and their forum
> doesn't work for me.
> Maybe somebody here has a clue?
> Or maybe this is even motherboard specific?
>
> To reproduce:
> $ aplay -Dhw:0 -fdat /dev/zero
>
> On a sane system (or here in PIC Mode) you'll see
> around 12 Interrupts/s.
> Here I see 24.
i think this is an effect of the 'POST-flush' symptom: the IO-APIC write
of unmasking the IRQ does not reach the chipset before the ACK via the
local-APIC does. Does it work fine if you artificially read after the
IO-APIC write?
Ingo
next prev parent reply other threads:[~2005-08-04 15:21 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-08-04 14:25 Karsten Wiese
2005-08-04 15:19 ` Ingo Molnar [this message]
2005-08-04 16:45 ` Karsten Wiese
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