[I2C] question on adapter design

[I2C] question on adapter design

[moreau francis]

I'm about writing a I2C bus adapter driver and wondering if it worth
to use interrupt for transfering data on the bus or just polling is
good enough ?

My hardware has a 8 bytes fifo for both Tx/Rx. It can generates
an interrupt when Tx fifo is empty and Rx fifo is not empty, 
actually like any UARTs. My CPU speed is 96 Mhz.

Thanks for your advices

Francis

Re: [I2C] question on adapter design

[Matti Aarnio]

On Fri, May 19, 2006 at 08:42:45AM +0000, moreau francis wrote:
> I'm about writing a I2C bus adapter driver and wondering if it worth
> to use interrupt for transfering data on the bus or just polling is
> good enough ?
> 
> My hardware has a 8 bytes fifo for both Tx/Rx. It can generates
> an interrupt when Tx fifo is empty and Rx fifo is not empty, 
> actually like any UARTs. My CPU speed is 96 Mhz.

The I²C (TM Philips) -bus runs at 100 kHz or (high-speed one) at 400 kHz.
An eight bit byte goes thru it in 80 or 20 microseconds depending on used
speed.  If your interrupt processing considers it as medium level
priority and fills the Tx fifo with as much as is available (most I²C TX
sequences do fit inside the 8 byte fifo) and collects as much data as is
available in the Rx fifo, you should be well set.

Most notable detail there is, that you do have those (for I²C) huge FIFOs.
Another thing is (I haven't verified this) that I²C master controls the
bus clock, and can stop it temporarily, when Tx FIFO is empty, or Rx FIFO
is full.

> Thanks for your advices
> Francis

/Matti Aarnio

Re : [I2C] question on adapter design

[moreau francis]

>The I²C (TM Philips) -bus runs at 100 kHz or (high-speed one) at 400 kHz.
>An eight bit byte goes thru it in 80 or 20 microseconds depending on used
>speed.  If your interrupt processing considers it as medium level
>priority and fills the Tx fifo with as much as is available (most I²C TX
>sequences do fit inside the 8 byte fifo) and collects as much data as is
>available in the Rx fifo, you should be well set.

ok so most of I2C commands shouldn't last more than 160 us when bus 
runs at 400 khz, right ? If so, I'm not sure it worth to use interrupts because
an active polling would avoid context switch that is not negligible in that case.
Interrupts can be usefull if I2C transfers would be longer than 8 bytes...

>
>Most notable detail there is, that you do have those (for I²C) huge FIFOs.
>Another thing is (I haven't verified this) that I²C master controls the
>bus clock, and can stop it temporarily, when Tx FIFO is empty, or Rx FIFO
>is full.
>

Indeed, my controller can automatically stop the bus clock when Tx fifo is
empty or Rx fifo is full.


Francis