[PATCH] spi_mpc83xx.c underclocking hotfix

[PATCH] spi_mpc83xx.c underclocking hotfix

[Clifford Wolf]

[-- Attachment #1: Type: text/plain, Size: 700 bytes --]

Hi kumar (spi_mpc83xx maintainer), Hi list,

the MPC83xx SPI controller clock divider can divide the system clock by not
more then 1024. The spi_mpc83xx driver does not check this and silently
writes garbage to the SPI controller registers when asked to run at lower
frequencies. I've tried to run the SPI on a 266MHz MPC8349E with 100kHz for
debugging a bus problem and suddenly was confronted with a 2nd problem to
debug..  ;-)

The attached patch adds an additional check which avoids writing garbage to
the SPI controller registers and warn the user about it. This might help
others to avoid simmilar problems.

yours,
 - clifford

-- 
Hardware /nm./: the part of the computer that you can kick.

[-- Attachment #2: spi_mpc83xx_hotfix.patch --]
[-- Type: text/plain, Size: 691 bytes --]

Index: drivers/spi/spi_mpc83xx.c
===================================================================
--- drivers/spi/spi_mpc83xx.c	(revision 170)
+++ drivers/spi/spi_mpc83xx.c	(working copy)
@@ -158,6 +158,12 @@
 
 		if ((mpc83xx_spi->sysclk / spi->max_speed_hz) >= 64) {
 			u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 64);
+			if (pm > 0x0f) {
+				printk(KERN_WARNING "MPC83xx SPI: SPICLK can't be less then a SYSCLK/1024!\n"
+						"Requested SPICLK is %d Hz. Will use %d Hz instead.\n",
+						spi->max_speed_hz, mpc83xx_spi->sysclk / 1024);
+				pm = 0x0f;
+			}
 			regval |= SPMODE_PM(pm) | SPMODE_DIV16;
 		} else {
 			u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 4);