From: Stephane Eranian <eranian@hpl.hp.com>
To: oprofile-list@lists.sourceforge.net
Cc: wcohen@redhat.com, ak@suse.de, perfmon@napali.hpl.hp.com,
linux-kernel@vger.kernel.org, levon@movementarian.org
Subject: OProfile issues
Date: Tue, 12 Jun 2007 08:02:46 -0700 [thread overview]
Message-ID: <20070612150246.GJ32163@frankl.hpl.hp.com> (raw)
Hello,
I am working on perfmon2 to allow Oprofile and perfmon2 to co-exist
as suggested by Andi Kleen. I looked at the Oprofile init/shutdown
code and I am puzzled by several things which you might be able to
explain for me. I am looking at 2.6.22-rc3.
Here are the issues:
* model->fill_in_addresses is called once for all CPUs
on X86, it does more than just filling in the addresses,
it also coordinates with the NMI watchdog by reserving
registers via the reserve_*nmi() interface.
The problem is that the release of the registers is done
in model->shutdown() which happens to be executed on every
CPU. So you end up releasing the registers too many times.
This is *not* harmless once you start sharing the PMU with
other subsystems given the way the allocator is designed.
* allocate_msrs() allocates two tables per CPU. One for the
counters, the other for the eventsel registers. But then
nmi_setup() copies the cpu_msrs[0] into cpu_msrs[] of all
other cpus. This operation overrides the cpu_msrs[].counters
and cpu_msrs[].controls pointers for all CPUs but CPU0.
But free_msrs() will free the same tables multiple times. This
causes a kernel dump when you enable certain kernel debugging
features. The fix is to copy the content of the counters and
controls array, not the pointers.
* the fill_in_addresses() callback for X86 invokes the NMI watchdog
reserve_*_nmi() register allocation routines. This is done regardless
of whether the NMI watchdog is active. When the NMI watchdog is not
active, the allocator will satisfy the allocation for the first MSR
of each type (counter or control), but then it will reject any
request for the others. You end up working with a single
counter/control register.
Are those known bugs?
--
-Stephane
next reply other threads:[~2007-06-12 15:03 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-06-12 15:02 Stephane Eranian [this message]
2007-06-12 18:37 ` Chris Wright
2007-06-12 18:38 ` Chuck Ebbert
2007-06-12 19:07 ` Björn Steinbrink
2007-06-13 1:41 ` [PATCH] Separate performance counter reservation from nmi watchdog Björn Steinbrink
2007-06-13 16:46 ` Björn Steinbrink
2007-06-18 9:52 ` Stephane Eranian
2007-06-18 10:32 ` Björn Steinbrink
[not found] ` <11823357571842-git-send-email->
2007-06-20 10:35 ` [PATCH 1/2] Separate the performance counter allocation from the LAPIC NMI watchdog Björn Steinbrink
2007-06-20 10:35 ` [PATCH 2/2] Finish separation of the performance counter allocator from the " Björn Steinbrink
2007-06-20 12:31 ` [PATCH 1/2] Separate the performance counter allocation from the LAPIC " Andi Kleen
2007-06-20 12:49 ` [perfmon] " Stephane Eranian
2007-06-20 13:01 ` Andi Kleen
2007-06-20 18:33 ` Björn Steinbrink
2007-06-20 18:34 ` [PATCH 1/2] Always probe the " Björn Steinbrink
2007-06-25 19:09 ` Andrew Morton
2007-06-25 19:36 ` Andi Kleen
2007-06-25 20:01 ` Stephane Eranian
2007-06-25 20:36 ` Andi Kleen
2007-06-25 21:04 ` Björn Steinbrink
2007-06-25 21:06 ` Björn Steinbrink
2007-06-20 18:35 ` [PATCH 2/2] Reserve the right performance counter for the Intel PerfMon " Björn Steinbrink
2007-06-20 21:59 ` [perfmon] Re: [PATCH 1/2] Separate the performance counter allocation from the LAPIC " Stephane Eranian
2007-06-21 8:36 ` Stephane Eranian
2007-06-22 7:13 ` Björn Steinbrink
2007-06-22 10:02 ` Stephane Eranian
2007-06-20 13:18 ` Björn Steinbrink
2007-06-20 10:49 ` [PATCH 0/2] Performance counter allocator separation Björn Steinbrink
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