From: Nick Piggin <nickpiggin@yahoo.com.au>
To: Linus Torvalds <torvalds@linux-foundation.org>
Cc: ak@suse.de, Jesse Barnes <jesse.barnes@intel.com>,
linux-kernel@vger.kernel.org
Subject: Re: Intel Memory Ordering White Paper
Date: Sat, 8 Sep 2007 04:13:12 +1000 [thread overview]
Message-ID: <200709080413.12282.nickpiggin@yahoo.com.au> (raw)
In-Reply-To: <200709090348.28076.nickpiggin@yahoo.com.au>
On Sunday 09 September 2007 03:48, Nick Piggin wrote:
> There is some suggestion in the source code that non-temporal stores
> (movntq) are weakly ordered. But AFAIKS from the documents, it is ordered
> when operating on wb memory. What's the situation there?
Sorry, it looks from the AMD document like nontemporal stores to wb
memory can go out of order. It is a bit hard to decipher what the types
mean.
If this is the case, we can either retain the sfence in smp_wmb(), or noop
it, and put explicit sfences around any place that performs nontemporal
stores...
Anyway, the lfence should be able to go away without so much trouble.
next prev parent reply other threads:[~2007-09-08 8:15 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-09-07 22:26 Jesse Barnes
2007-09-08 8:54 ` Nick Piggin
2007-09-07 23:20 ` Linus Torvalds
2007-09-08 17:34 ` Nick Piggin
2007-09-08 17:48 ` Nick Piggin
2007-09-07 18:13 ` Nick Piggin [this message]
2007-09-08 8:53 ` Andi Kleen
2007-09-07 19:57 ` Nick Piggin
2007-09-08 10:19 ` Andi Kleen
2007-09-07 20:32 ` Nick Piggin
2007-09-08 20:37 ` H. Peter Anvin
2007-09-08 11:34 ` dean gaudet
2007-09-08 12:08 ` Petr Vandrovec
2007-09-08 12:27 ` dean gaudet
2007-09-08 10:30 ` Alan Cox
2007-09-07 20:46 ` Nick Piggin
2007-09-08 10:29 ` Alan Cox
2007-09-07 20:49 ` Nick Piggin
2007-09-08 14:11 ` Alan Cox
2007-09-12 18:26 ` Dr. David Alan Gilbert
2007-09-19 16:26 ` Jesse Barnes
2007-09-19 17:29 ` Andi Kleen
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