From: Alan Cox <alan@lxorguk.ukuu.org.uk>
To: Jesse Barnes <jesse.barnes@intel.com>
Cc: linux-kernel@vger.kernel.org
Subject: Re: Intel Memory Ordering White Paper
Date: Sat, 8 Sep 2007 11:29:22 +0100 [thread overview]
Message-ID: <20070908112922.3fd41adc@the-village.bc.nu> (raw)
In-Reply-To: <200709071526.51169.jesse.barnes@intel.com>
On Fri, 7 Sep 2007 15:26:50 -0700
Jesse Barnes <jesse.barnes@intel.com> wrote:
> FYI, we just released a new white paper describing memory ordering for
> Intel processors:
> http://developer.intel.com/products/processor/manuals/index.htm
>
> Should help answer some questions about some of the ordering primitives
> we use on i386 and x86_64.
Nice - but it appears to be 64bit only - and indeed it appears to be
untrue for real 32bit because of the Pentium Pro fencing errata.
The kernel also runs on IDT Winchip, Cyrix and AMD processors not all of
which have exactly the same behaviour (the IDT Winchip as we run it
profoundly differs)
Alan
next prev parent reply other threads:[~2007-09-08 10:21 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-09-07 22:26 Jesse Barnes
2007-09-08 8:54 ` Nick Piggin
2007-09-07 23:20 ` Linus Torvalds
2007-09-08 17:34 ` Nick Piggin
2007-09-08 17:48 ` Nick Piggin
2007-09-07 18:13 ` Nick Piggin
2007-09-08 8:53 ` Andi Kleen
2007-09-07 19:57 ` Nick Piggin
2007-09-08 10:19 ` Andi Kleen
2007-09-07 20:32 ` Nick Piggin
2007-09-08 20:37 ` H. Peter Anvin
2007-09-08 11:34 ` dean gaudet
2007-09-08 12:08 ` Petr Vandrovec
2007-09-08 12:27 ` dean gaudet
2007-09-08 10:30 ` Alan Cox
2007-09-07 20:46 ` Nick Piggin
2007-09-08 10:29 ` Alan Cox [this message]
2007-09-07 20:49 ` Nick Piggin
2007-09-08 14:11 ` Alan Cox
2007-09-12 18:26 ` Dr. David Alan Gilbert
2007-09-19 16:26 ` Jesse Barnes
2007-09-19 17:29 ` Andi Kleen
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