[PATCH] [1/2] Fix some inaccurate comments in MTRR checking code

[PATCH] [1/2] Fix some inaccurate comments in MTRR checking code

[Andi Kleen]

- is_cpu(INTEL) actually refers only to the MTRR architecture
and all AMD CPUs since K7 use the Intel MTRR architecture so the
fixup code runs on AMD too. Remove a comment claiming otherwise.

[Perhaps is_cpu should be renamed, the name is clearly confusing]

- Clarify another incorrect comment.

Cc: davej@codemonkey.org.uk
Signed-off-by: Andi Kleen <ak@suse.de>

---
 arch/x86/kernel/cpu/mtrr/main.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Index: linux/arch/x86/kernel/cpu/mtrr/main.c
===================================================================
--- linux.orig/arch/x86/kernel/cpu/mtrr/main.c
+++ linux/arch/x86/kernel/cpu/mtrr/main.c
@@ -640,6 +640,8 @@ early_param("disable_mtrr_trim", disable
  * Some buggy BIOSes don't setup the MTRRs properly for systems with certain
  * memory configurations.  This routine checks to make sure the MTRRs having
  * a write back type cover all of the memory the kernel is intending to use.
+ * [AK: actually it doesn't check that. It just checks that the highest
+ * MTRR is matching the end of memory. That is not quite the same.]
  * If not, it'll trim any memory off the end by adjusting end_pfn, removing
  * it from the kernel's allocation pools, warning the user with an obnoxious
  * message.
@@ -649,7 +651,6 @@ void __init mtrr_trim_uncached_memory(vo
 	unsigned long i, base, size, highest_addr = 0, def, dummy;
 	mtrr_type type;
 
-	/* Make sure we only trim uncachable memory on Intel machines */
 	rdmsr(MTRRdefType_MSR, def, dummy);
 	def &= 0xff;
 	if (!is_cpu(INTEL) || disable_mtrr_trim || def != MTRR_TYPE_UNCACHABLE)

[PATCH] [2/2] Fix MTRR check on AMD systems with > 4GB RAM

[Andi Kleen]

Newer AMD systems (since K8RevF) have a magic SYSCFG MSR bit to force WB
on memory beyond 4GB. This is not reflected in the standard MTRR
MSRs, so the MTRR checking routine would get confused and disable
perfectly good RAM beyond 4GB. Implement code for checking that bit.


Signed-off-by: Andi Kleen <ak@suse.de>

---
 arch/x86/kernel/cpu/mtrr/main.c |   34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

Index: linux/arch/x86/kernel/cpu/mtrr/main.c
===================================================================
--- linux.orig/arch/x86/kernel/cpu/mtrr/main.c
+++ linux/arch/x86/kernel/cpu/mtrr/main.c
@@ -634,6 +634,37 @@ static int __init disable_mtrr_trim_setu
 early_param("disable_mtrr_trim", disable_mtrr_trim_setup);
 
 #ifdef CONFIG_X86_64
+
+/*
+ * Newer AMD K8s and later CPUs have a special magic MSR way to force WB
+ * for memory >4GB. Check for that here.
+ * Note this won't check if the MTRRs < 4GB where the magic bit doesn't
+ * apply to are wrong, but so far we don't know of any such case in the wild.
+ */
+
+#define Tom2ForceMemTypeWB (1U << 22)
+static __init int amd_special_default_mtrr(void)
+{
+	u32 l, h;
+
+	/* Doesn't apply to memory < 4GB */
+	if (end_pfn <= (0xffffffff >> PAGE_SHIFT))
+		return 0;
+	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
+		return 0;
+	if (boot_cpu_data.x86 < 0xf || boot_cpu_data.x86 > 0x11)
+		return 0;
+	/* In case some hypervisor doesn't pass SYSCFG through */
+	if (rdmsr_safe(MSR_K8_SYSCFG, &l, &h) < 0)
+		return 0;
+	/* Memory between 4GB and top of mem is forced WB by this magic bit.
+	 * Reserved before K8RevF, but should be zero there.
+	 */
+	if (l & Tom2ForceMemTypeWB)
+		return 1;
+	return 0;
+}
+
 /**
  * mtrr_trim_uncached_memory - trim RAM not covered by MTRRs
  *
@@ -667,6 +698,9 @@ void __init mtrr_trim_uncached_memory(vo
 			highest_addr = base + size;
 	}
 
+	if (amd_special_default_mtrr())
+		return;
+
 	if ((highest_addr >> PAGE_SHIFT) < end_pfn) {
 		printk(KERN_WARNING "***************\n");
 		printk(KERN_WARNING "**** WARNING: likely BIOS bug\n");