* [patch 2/4] tip, dmar: context cache and IOTLB invalidation using queued invalidation
2008-10-08 21:01 [patch 0/4] tip, dmar: queued invalidation patches Suresh Siddha
2008-10-08 21:01 ` [patch 1/4] tip, dmar: use spin_lock_irqsave() in qi_submit_sync() Suresh Siddha
@ 2008-10-08 21:01 ` Suresh Siddha
2008-10-08 21:01 ` [patch 3/4] tip, dmar: Use queued invalidation interface for IOTLB and context invalidation Suresh Siddha
2008-10-08 21:01 ` [patch 4/4] tip, dmar: remove the quirk which disables dma-remapping when intr-remapping enabled Suresh Siddha
3 siblings, 0 replies; 5+ messages in thread
From: Suresh Siddha @ 2008-10-08 21:01 UTC (permalink / raw)
To: mingo; +Cc: linux-kernel, dwmw2, youquan.song, Suresh Siddha
[-- Attachment #1: qi_support_for_context_iotlb_invalidation.patch --]
[-- Type: text/plain, Size: 3875 bytes --]
From: Youquan Song <youquan.song@intel.com>
Subject: context cache and IOTLB invalidation using queued invalidation
Implement context cache invalidate and IOTLB invalidation using
queued invalidation interface. This interface will be used by
DMA remapping, when queued invalidation is supported.
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
---
Index: tip/drivers/pci/dmar.c
===================================================================
--- tip.orig/drivers/pci/dmar.c 2008-10-07 16:27:47.000000000 -0700
+++ tip/drivers/pci/dmar.c 2008-10-07 16:27:50.000000000 -0700
@@ -657,6 +657,62 @@
qi_submit_sync(&desc, iommu);
}
+int qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,
+ u64 type, int non_present_entry_flush)
+{
+
+ struct qi_desc desc;
+
+ if (non_present_entry_flush) {
+ if (!cap_caching_mode(iommu->cap))
+ return 1;
+ else
+ did = 0;
+ }
+
+ desc.low = QI_CC_FM(fm) | QI_CC_SID(sid) | QI_CC_DID(did)
+ | QI_CC_GRAN(type) | QI_CC_TYPE;
+ desc.high = 0;
+
+ qi_submit_sync(&desc, iommu);
+
+ return 0;
+
+}
+
+int qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
+ unsigned int size_order, u64 type,
+ int non_present_entry_flush)
+{
+ u8 dw = 0, dr = 0;
+
+ struct qi_desc desc;
+ int ih = 0;
+
+ if (non_present_entry_flush) {
+ if (!cap_caching_mode(iommu->cap))
+ return 1;
+ else
+ did = 0;
+ }
+
+ if (cap_write_drain(iommu->cap))
+ dw = 1;
+
+ if (cap_read_drain(iommu->cap))
+ dr = 1;
+
+ desc.low = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw)
+ | QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE;
+ desc.high = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih)
+ | QI_IOTLB_AM(size_order);
+
+ qi_submit_sync(&desc, iommu);
+
+ return 0;
+
+}
+
/*
* Enable Queued Invalidation interface. This is a must to support
* interrupt-remapping. Also used by DMA-remapping, which replaces
Index: tip/drivers/pci/intel-iommu.h
===================================================================
--- tip.orig/drivers/pci/intel-iommu.h 2008-10-07 15:42:47.000000000 -0700
+++ tip/drivers/pci/intel-iommu.h 2008-10-07 16:27:50.000000000 -0700
@@ -127,6 +127,7 @@
/* IOTLB_REG */
+#define DMA_TLB_FLUSH_GRANU_OFFSET 60
#define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
#define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
#define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
@@ -140,6 +141,7 @@
#define DMA_TLB_MAX_SIZE (0x3f)
/* INVALID_DESC */
+#define DMA_CCMD_INVL_GRANU_OFFSET 61
#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 3)
#define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 3)
#define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 3)
@@ -238,6 +240,19 @@
#define QI_IWD_STATUS_DATA(d) (((u64)d) << 32)
#define QI_IWD_STATUS_WRITE (((u64)1) << 5)
+#define QI_IOTLB_DID(did) (((u64)did) << 16)
+#define QI_IOTLB_DR(dr) (((u64)dr) << 7)
+#define QI_IOTLB_DW(dw) (((u64)dw) << 6)
+#define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
+#define QI_IOTLB_ADDR(addr) (((u64)addr) & PAGE_MASK_4K)
+#define QI_IOTLB_IH(ih) (((u64)ih) << 6)
+#define QI_IOTLB_AM(am) (((u8)am))
+
+#define QI_CC_FM(fm) (((u64)fm) << 48)
+#define QI_CC_SID(sid) (((u64)sid) << 32)
+#define QI_CC_DID(did) (((u64)did) << 16)
+#define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))
+
struct qi_desc {
u64 low, high;
};
@@ -303,5 +318,11 @@
extern int dmar_enable_qi(struct intel_iommu *iommu);
extern void qi_global_iec(struct intel_iommu *iommu);
+extern int qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
+ u8 fm, u64 type, int non_present_entry_flush);
+extern int qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
+ unsigned int size_order, u64 type,
+ int non_present_entry_flush);
+
extern void qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
#endif
--
^ permalink raw reply [flat|nested] 5+ messages in thread* [patch 3/4] tip, dmar: Use queued invalidation interface for IOTLB and context invalidation.
2008-10-08 21:01 [patch 0/4] tip, dmar: queued invalidation patches Suresh Siddha
2008-10-08 21:01 ` [patch 1/4] tip, dmar: use spin_lock_irqsave() in qi_submit_sync() Suresh Siddha
2008-10-08 21:01 ` [patch 2/4] tip, dmar: context cache and IOTLB invalidation using queued invalidation Suresh Siddha
@ 2008-10-08 21:01 ` Suresh Siddha
2008-10-08 21:01 ` [patch 4/4] tip, dmar: remove the quirk which disables dma-remapping when intr-remapping enabled Suresh Siddha
3 siblings, 0 replies; 5+ messages in thread
From: Suresh Siddha @ 2008-10-08 21:01 UTC (permalink / raw)
To: mingo; +Cc: linux-kernel, dwmw2, youquan.song, Suresh Siddha
[-- Attachment #1: unify_iommu_cache_invalidate.patch --]
[-- Type: text/plain, Size: 6868 bytes --]
From: Youquan Song <youquan.song@intel.com>
Subject: Use queued invalidation interface for IOTLB and context invalidation
If queued invalidation interface is available and enabled, queued invalidation
interface will be used instead of the register based interface.
According to Vt-d2 specification, when queued invalidation is enabled,
invalidation command submit works only through invalidation queue and not
through the command registers interface.
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
---
Index: tip/drivers/pci/intel-iommu.c
===================================================================
--- tip.orig/drivers/pci/intel-iommu.c 2008-10-08 11:24:31.000000000 -0700
+++ tip/drivers/pci/intel-iommu.c 2008-10-08 13:37:58.000000000 -0700
@@ -567,27 +567,6 @@
return 0;
}
-static int inline iommu_flush_context_global(struct intel_iommu *iommu,
- int non_present_entry_flush)
-{
- return __iommu_flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL,
- non_present_entry_flush);
-}
-
-static int inline iommu_flush_context_domain(struct intel_iommu *iommu, u16 did,
- int non_present_entry_flush)
-{
- return __iommu_flush_context(iommu, did, 0, 0, DMA_CCMD_DOMAIN_INVL,
- non_present_entry_flush);
-}
-
-static int inline iommu_flush_context_device(struct intel_iommu *iommu,
- u16 did, u16 source_id, u8 function_mask, int non_present_entry_flush)
-{
- return __iommu_flush_context(iommu, did, source_id, function_mask,
- DMA_CCMD_DEVICE_INVL, non_present_entry_flush);
-}
-
/* return value determine if we need a write buffer flush */
static int __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
u64 addr, unsigned int size_order, u64 type,
@@ -660,20 +639,6 @@
return 0;
}
-static int inline iommu_flush_iotlb_global(struct intel_iommu *iommu,
- int non_present_entry_flush)
-{
- return __iommu_flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH,
- non_present_entry_flush);
-}
-
-static int inline iommu_flush_iotlb_dsi(struct intel_iommu *iommu, u16 did,
- int non_present_entry_flush)
-{
- return __iommu_flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH,
- non_present_entry_flush);
-}
-
static int iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
u64 addr, unsigned int pages, int non_present_entry_flush)
{
@@ -684,8 +649,9 @@
/* Fallback to domain selective flush if no PSI support */
if (!cap_pgsel_inv(iommu->cap))
- return iommu_flush_iotlb_dsi(iommu, did,
- non_present_entry_flush);
+ return iommu->flush.flush_iotlb(iommu, did, 0, 0,
+ DMA_TLB_DSI_FLUSH,
+ non_present_entry_flush);
/*
* PSI requires page size to be 2 ^ x, and the base address is naturally
@@ -694,11 +660,12 @@
mask = ilog2(__roundup_pow_of_two(pages));
/* Fallback to domain selective flush if size is too big */
if (mask > cap_max_amask_val(iommu->cap))
- return iommu_flush_iotlb_dsi(iommu, did,
- non_present_entry_flush);
+ return iommu->flush.flush_iotlb(iommu, did, 0, 0,
+ DMA_TLB_DSI_FLUSH, non_present_entry_flush);
- return __iommu_flush_iotlb(iommu, did, addr, mask,
- DMA_TLB_PSI_FLUSH, non_present_entry_flush);
+ return iommu->flush.flush_iotlb(iommu, did, addr, mask,
+ DMA_TLB_PSI_FLUSH,
+ non_present_entry_flush);
}
static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
@@ -1204,11 +1171,13 @@
__iommu_flush_cache(iommu, context, sizeof(*context));
/* it's a non-present to present mapping */
- if (iommu_flush_context_device(iommu, domain->id,
- (((u16)bus) << 8) | devfn, DMA_CCMD_MASK_NOBIT, 1))
+ if (iommu->flush.flush_context(iommu, domain->id,
+ (((u16)bus) << 8) | devfn, DMA_CCMD_MASK_NOBIT,
+ DMA_CCMD_DEVICE_INVL, 1))
iommu_flush_write_buffer(iommu);
else
- iommu_flush_iotlb_dsi(iommu, 0, 0);
+ iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH, 0);
+
spin_unlock_irqrestore(&iommu->lock, flags);
return 0;
}
@@ -1310,8 +1279,10 @@
static void detach_domain_for_dev(struct dmar_domain *domain, u8 bus, u8 devfn)
{
clear_context_table(domain->iommu, bus, devfn);
- iommu_flush_context_global(domain->iommu, 0);
- iommu_flush_iotlb_global(domain->iommu, 0);
+ domain->iommu->flush.flush_context(domain->iommu, 0, 0, 0,
+ DMA_CCMD_GLOBAL_INVL, 0);
+ domain->iommu->flush.flush_iotlb(domain->iommu, 0, 0, 0,
+ DMA_TLB_GLOBAL_FLUSH, 0);
}
static void domain_remove_dev_info(struct dmar_domain *domain)
@@ -1662,6 +1633,28 @@
}
}
+ for_each_drhd_unit(drhd) {
+ if (drhd->ignored)
+ continue;
+
+ iommu = drhd->iommu;
+ if (dmar_enable_qi(iommu)) {
+ /*
+ * Queued Invalidate not enabled, use Register Based
+ * Invalidate
+ */
+ iommu->flush.flush_context = __iommu_flush_context;
+ iommu->flush.flush_iotlb = __iommu_flush_iotlb;
+ printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
+ "invalidation\n", drhd->reg_base_addr);
+ } else {
+ iommu->flush.flush_context = qi_flush_context;
+ iommu->flush.flush_iotlb = qi_flush_iotlb;
+ printk(KERN_INFO "IOMMU 0x%Lx: using Queued"
+ "invalidation\n", drhd->reg_base_addr);
+ }
+ }
+
/*
* For each rmrr
* for each dev attached to rmrr
@@ -1714,9 +1707,10 @@
iommu_set_root_entry(iommu);
- iommu_flush_context_global(iommu, 0);
- iommu_flush_iotlb_global(iommu, 0);
-
+ iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL,
+ 0);
+ iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH,
+ 0);
iommu_disable_protect_mem_regions(iommu);
ret = iommu_enable_translation(iommu);
@@ -1891,7 +1885,8 @@
struct intel_iommu *iommu =
deferred_flush[i].domain[0]->iommu;
- iommu_flush_iotlb_global(iommu, 0);
+ iommu->flush.flush_iotlb(iommu, 0, 0, 0,
+ DMA_TLB_GLOBAL_FLUSH, 0);
for (j = 0; j < deferred_flush[i].next; j++) {
__free_iova(&deferred_flush[i].domain[j]->iovad,
deferred_flush[i].iova[j]);
Index: tip/drivers/pci/intel-iommu.h
===================================================================
--- tip.orig/drivers/pci/intel-iommu.h 2008-10-08 13:33:41.000000000 -0700
+++ tip/drivers/pci/intel-iommu.h 2008-10-08 13:33:43.000000000 -0700
@@ -278,6 +278,13 @@
};
#endif
+struct iommu_flush {
+ int (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,
+ u64 type, int non_present_entry_flush);
+ int (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
+ unsigned int size_order, u64 type, int non_present_entry_flush);
+};
+
struct intel_iommu {
void __iomem *reg; /* Pointer to hardware regs, virtual addr */
u64 cap;
@@ -297,6 +304,7 @@
unsigned char name[7]; /* Device Name */
struct msi_msg saved_msg;
struct sys_device sysdev;
+ struct iommu_flush flush;
#endif
struct q_inval *qi; /* Queued invalidation info */
#ifdef CONFIG_INTR_REMAP
--
^ permalink raw reply [flat|nested] 5+ messages in thread