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From: Andi Kleen <andi@firstfloor.org>
To: akpm@linux-foundation.org, mingo@elte.hu, tglx@linutronix.de,
	hpa@zytor.com, linux-kernel@vger.kernel.org
Subject: [PATCH] [5/9] x86: CMCI: Use polled banks bitmap in machine check poller
Date: Thu, 12 Feb 2009 13:49:34 +0100 (CET)	[thread overview]
Message-ID: <20090212124934.532233E666D@basil.firstfloor.org> (raw)
In-Reply-To: <20090212149.227733077@firstfloor.org>


Define a per cpu bitmap that contains the banks polled by the machine
check poller. This is needed for the CMCI code in the next patches
to be able to disable polling on specific banks.

The bank by default contains all banks, so there is no behaviour
change. Only future code will remove some banks from the polling
set.

Signed-off-by: Andi Kleen <ak@linux.intel.com>

---
 arch/x86/include/asm/mce.h              |    5 ++++-
 arch/x86/kernel/cpu/mcheck/mce_64.c     |   16 ++++++++++++----
 arch/x86/kernel/cpu/mcheck/mce_amd_64.c |    3 ++-
 3 files changed, 18 insertions(+), 6 deletions(-)

Index: linux/arch/x86/include/asm/mce.h
===================================================================
--- linux.orig/arch/x86/include/asm/mce.h	2009-02-12 11:30:51.000000000 +0100
+++ linux/arch/x86/include/asm/mce.h	2009-02-12 12:10:17.000000000 +0100
@@ -119,11 +119,14 @@
 
 extern void do_machine_check(struct pt_regs *, long);
 
+typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
+DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
+
 enum mcp_flags {
 	MCP_TIMESTAMP = (1 << 0),	/* log time stamp */
 	MCP_UC = (1 << 1),		/* log uncorrected errors */
 };
-extern void machine_check_poll(enum mcp_flags flags);
+extern void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
 
 extern int mce_notify_user(void);
 
Index: linux/arch/x86/kernel/cpu/mcheck/mce_64.c
===================================================================
--- linux.orig/arch/x86/kernel/cpu/mcheck/mce_64.c	2009-02-12 11:30:51.000000000 +0100
+++ linux/arch/x86/kernel/cpu/mcheck/mce_64.c	2009-02-12 12:10:17.000000000 +0100
@@ -62,6 +62,11 @@
 
 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
 
+/* MCA banks polled by the period polling timer for corrected events */
+DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
+	[0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
+};
+
 /* Do initial initialization of a struct mce */
 void mce_setup(struct mce *m)
 {
@@ -191,7 +196,7 @@
  *
  * This is executed in standard interrupt context.
  */
-void machine_check_poll(enum mcp_flags flags)
+void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
 {
 	struct mce m;
 	int i;
@@ -200,7 +205,7 @@
 
 	rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus);
 	for (i = 0; i < banks; i++) {
-		if (!bank[i])
+		if (!bank[i] || !test_bit(i, *b))
 			continue;
 
 		m.misc = 0;
@@ -458,7 +463,8 @@
 	WARN_ON(smp_processor_id() != data);
 
 	if (mce_available(&current_cpu_data))
-		machine_check_poll(MCP_TIMESTAMP);
+		machine_check_poll(MCP_TIMESTAMP,
+				&__get_cpu_var(mce_poll_banks));
 
 	/*
 	 * Alert userspace if needed.  If we logged an MCE, reduce the
@@ -567,11 +573,13 @@
 {
 	u64 cap;
 	int i;
+	mce_banks_t all_banks;
 
 	/*
 	 * Log the machine checks left over from the previous reset.
 	 */
-	machine_check_poll(MCP_UC);
+	bitmap_fill(all_banks, MAX_NR_BANKS);
+	machine_check_poll(MCP_UC, &all_banks);
 
 	set_in_cr4(X86_CR4_MCE);
 
Index: linux/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
===================================================================
--- linux.orig/arch/x86/kernel/cpu/mcheck/mce_amd_64.c	2009-02-12 11:30:51.000000000 +0100
+++ linux/arch/x86/kernel/cpu/mcheck/mce_amd_64.c	2009-02-12 11:30:51.000000000 +0100
@@ -231,7 +231,8 @@
 
 			/* Log the machine check that caused the threshold
 			   event. */
-			machine_check_poll(MCP_TIMESTAMP);
+			machine_check_poll(MCP_TIMESTAMP,
+					&__get_cpu_var(mce_poll_banks));
 
 			if (high & MASK_OVERFLOW_HI) {
 				rdmsrl(address, m.misc);

  parent reply	other threads:[~2009-02-12 12:52 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-02-12 12:49 [PATCH] [0/9] x86: CMCI: Add support for Intel CMCI Andi Kleen
2009-02-12 12:49 ` [PATCH] [1/9] x86: CMCI: Export MAX_NR_BANKS Andi Kleen
2009-02-12 12:49 ` [PATCH] [2/9] x86: CMCI: Factor out threshold interrupt handler Andi Kleen
2009-02-12 12:49 ` [PATCH] [3/9] x86: CMCI: Avoid potential reentry of threshold interrupt Andi Kleen
2009-02-12 12:49 ` [PATCH] [4/9] x86: MCE: Replace machine check events logged interval with ratelimit Andi Kleen
2009-02-12 12:49 ` Andi Kleen [this message]
2009-02-12 12:49 ` [PATCH] [6/9] x86: CMCI: Define MSR names and fields for new CMCI registers Andi Kleen
2009-02-12 12:49 ` [PATCH] [7/9] x86: CMCI: Add CMCI support Andi Kleen
2009-02-12 12:49 ` [PATCH] [8/9] x86: CMCI: Disable CMCI on rebooting Andi Kleen
2009-02-12 12:49 ` [PATCH] [9/9] x86: CMCI: Recheck CMCI banks after APIC has been enabled on CPU #0 Andi Kleen

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