From: Andreas Herrmann <andreas.herrmann3@amd.com>
To: Andi Kleen <andi@firstfloor.org>
Cc: Ingo Molnar <mingo@elte.hu>, "H. Peter Anvin" <hpa@zytor.com>,
Thomas Gleixner <tglx@linutronix.de>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/3] x86: adapt CPU topology detection for AMD Magny-Cours
Date: Tue, 5 May 2009 11:22:38 +0200 [thread overview]
Message-ID: <20090505092238.GB29045@alberich.amd.com> (raw)
In-Reply-To: <87vdogbp4g.fsf@basil.nowhere.org>
On Mon, May 04, 2009 at 10:16:15PM +0200, Andi Kleen wrote:
> Andreas Herrmann <andreas.herrmann3@amd.com> writes:
>
> > Following patches add support for AMD Magny-Cours CPU.
> >
> > I slightly change struct cpuinfo where I'd like to introduce
> > cpu_node_id to reflect CPU topology for AMD Magny-Cours CPU which
> > consists of two internal-nodes.
>
> It's unclear to me why you need this special case versus
> just using the normal NUMA distances to represent the internal
> nodes as "nearby nodes" versus sockets as "farer away".
NUMA memory allocation and scheduling based on SRAT works just fine
w/o that fix. But the patches are _not_ for NUMA node detection.
This is for CPU topology detection -- which cores are using the same
northbridge.
> Essentially it should be just two level NUMA which can be already
> described fine for the scheduler or VM using the existing SRAT
> mechanism.
It doesn't suffice to rely on SRAT here.
Best example is node interleaving. Usually you won't get a SRAT table
on such a system. Thus you see just one NUMA node in
/sys/devices/system/node. But on such a configuration you still see
(and you want to see) the correct CPU topology information in
/sys/devices/system/cpu/cpuX/topology. Based on that you always can
figure out which cores are on the same physical package independent of
availability and contents of SRAT and even with kernels that are
compiled w/o NUMA support.
A big change with Magny-Cours in contrast to other AMD
CPUs is that instead of
physical package == one northbridge (one node)
we have
physical package == two northbridges (two nodes)
and this needs to be represented somehow in the kernel.
> Who needs this additional information?
The kernel needs to know this when accessing processor configuration
space, when accessing shared MSRs or for counting northbridge specific
events.
Regards,
Andreas
--
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System | Karl-Hammerschmidt-Str. 34, 85609 Dornach b. München, Germany
Research | Geschäftsführer: Thomas M. McCoy, Giuliano Meroni
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next prev parent reply other threads:[~2009-05-05 9:23 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-05-04 17:33 Andreas Herrmann
2009-05-04 17:34 ` [PATCH 1/3] x86: introduce cpuinfo->cpu_node_id to reflect topology of multi-node CPU Andreas Herrmann
2009-05-06 11:44 ` Ingo Molnar
2009-05-06 16:14 ` Andreas Herrmann
2009-05-04 17:36 ` [PATCH 2/3] x86: fixup topology detection for AMD " Andreas Herrmann
2009-05-04 17:37 ` [PATCH 3/3] x86: cacheinfo: fixup L3 cache information " Andreas Herrmann
2009-05-04 17:44 ` [PATCH 0/3] x86: adapt CPU topology detection for AMD Magny-Cours Andreas Herrmann
2009-05-04 20:16 ` Andi Kleen
2009-05-05 9:22 ` Andreas Herrmann [this message]
2009-05-05 9:35 ` Andi Kleen
2009-05-05 10:48 ` Andreas Herrmann
2009-05-05 12:02 ` Andi Kleen
2009-05-05 14:40 ` Andreas Herrmann
2009-05-05 15:31 ` Andi Kleen
2009-05-05 16:47 ` Andreas Herrmann
2009-05-05 17:54 ` Andi Kleen
2009-05-08 14:28 ` Andreas Herrmann
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