* [RFC] Load cache_aligned sections, cache aligned (VIA, some Intel, others?)
@ 2009-06-15 15:59 Michael S. Zick
0 siblings, 0 replies; only message in thread
From: Michael S. Zick @ 2009-06-15 15:59 UTC (permalink / raw)
To: Linux Kernel Mailing List; +Cc: Harald Welte
The expected size of the processor cache line size is set
in the Kbuild menu by selection of the processor (sort-of).
How about telling the loader to cache-line align the cache_aligned sections?
This define comes in via (no pun intended): arch/x86/include/asm/cache.h
diff --git a/arch/x86/kernel/vmlinux_32.lds.S b/arch/x86/kernel/vmlinux_32.lds.S
index 62ad500..26f68a5 100644
--- a/arch/x86/kernel/vmlinux_32.lds.S
+++ b/arch/x86/kernel/vmlinux_32.lds.S
@@ -82,7 +82,7 @@ SECTIONS
*(.data.idt)
}
- . = ALIGN(32);
+ . = ALIGN(L1_CACHE_BYTES);
.data.cacheline_aligned : AT(ADDR(.data.cacheline_aligned) - LOAD_OFFSET) {
*(.data.cacheline_aligned)
}
Mike
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2009-06-15 15:59 [RFC] Load cache_aligned sections, cache aligned (VIA, some Intel, others?) Michael S. Zick
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