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From: Hans Rosenfeld <hans.rosenfeld@amd.com>
To: Ingo Molnar <mingo@elte.hu>
Cc: "hpa@zytor.com" <hpa@zytor.com>,
	"tglx@linutronix.de" <tglx@linutronix.de>,
	"Herrmann3, Andreas" <Andreas.Herrmann3@amd.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"x86@kernel.org" <x86@kernel.org>
Subject: Re: [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs
Date: Wed, 26 Jan 2011 18:05:32 +0100	[thread overview]
Message-ID: <20110126170532.GG877@escobedo.osrc.amd.com> (raw)
In-Reply-To: <20110126105637.GA27809@elte.hu>

On Wed, Jan 26, 2011 at 05:56:37AM -0500, Ingo Molnar wrote:
> 
> * Hans Rosenfeld <hans.rosenfeld@amd.com> wrote:
> 
> > L3 Cache Partitioning allows selecting which of the 4 L3 subcaches can
> > be used for evictions by the L2 cache of each compute unit. By writing a
> > 4-bit hexadecimal mask into the the sysfs file /sys/devices/system/cpu/\
> > cpuX/cache/index3/subcaches, the user can set the enabled subcaches for
> > a CPU. The settings are directly read from and written to the hardware,
> > so there is no way to have contradicting settings for two CPUs belonging
> > to the same compute unit. Writing will always overwrite any previous
> > setting for a compute unit.
> > 
> > Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com>
> > ---
> >  arch/x86/include/asm/amd_nb.h         |    3 +
> >  arch/x86/kernel/amd_nb.c              |   55 +++++++++++++++++++++++++
> >  arch/x86/kernel/cpu/intel_cacheinfo.c |   73 +++++++++++++++++++++++++++-----
> >  3 files changed, 119 insertions(+), 12 deletions(-)
> 
> I have picked up the other 3 patches, but this one causes this build failure:
> 
>  arch/x86/kernel/amd_nb.c: In function ?amd_get_subcaches?:
>  arch/x86/kernel/amd_nb.c:129:36: error: ?struct cpuinfo_x86? has no member named ?compute_unit_id?
>  arch/x86/kernel/amd_nb.c: In function ?amd_set_subcaches?:
>  arch/x86/kernel/amd_nb.c:154:28: error: ?struct cpuinfo_x86? has no member named ?compute_unit_id?
>  arch/x86/kernel/amd_nb.c:155:36: error: ?struct cpuinfo_x86? has no member named ?compute_unit_id?
>  arch/x86/kernel/amd_nb.c: In function ?amd_get_subcaches?:
>  arch/x86/kernel/amd_nb.c:130:1: warning: control reaches end of non-void function

Hrmpf. CONFIG_SMP.

Sorry for the noise, fixed patch will follow shortly.


Hans


-- 
%SYSTEM-F-ANARCHISM, The operating system has been overthrown


  reply	other threads:[~2011-01-26 17:05 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-01-24 15:05 [PATCH 0/4] x86, amd: family 0x15 L3 cache features Hans Rosenfeld
2011-01-24 15:05 ` [PATCH 1/4] x86, amd: Normalize compute unit IDs on multi-node processors Hans Rosenfeld
2011-01-26 10:57   ` [tip:x86/amd-nb] " tip-bot for Andreas Herrmann
2011-02-14 14:30     ` Ingo Molnar
2011-02-14 17:14       ` [PATCH] x86, amd: Fix uninitialized variable warning Borislav Petkov
2011-02-15  3:10         ` [tip:x86/amd-nb] x86, amd: Initialize variable properly tip-bot for Borislav Petkov
2011-02-04 22:07   ` [PATCH 1/4] x86, amd: Normalize compute unit IDs on multi-node processors Andrew Morton
2011-01-24 15:05 ` [PATCH 2/4] x86, amd: Enable L3 cache index disable on family 0x15 Hans Rosenfeld
2011-01-26 10:58   ` [tip:x86/amd-nb] " tip-bot for Hans Rosenfeld
2011-01-24 15:05 ` [PATCH 3/4] x86, amd: Extend AMD northbridge caching code to support "Link Control" devices Hans Rosenfeld
2011-01-26 10:58   ` [tip:x86/amd-nb] " tip-bot for Hans Rosenfeld
2011-01-24 15:05 ` [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs Hans Rosenfeld
2011-01-26 10:56   ` Ingo Molnar
2011-01-26 17:05     ` Hans Rosenfeld [this message]
2011-01-26 17:08     ` Hans Rosenfeld
2011-01-26 20:56       ` Ingo Molnar
2011-01-27 11:50         ` Hans Rosenfeld
2011-01-27 12:47           ` Ingo Molnar
2011-02-01 15:14             ` Hans Rosenfeld
2011-02-07 17:10             ` Hans Rosenfeld
2011-02-08 12:03               ` [tip:x86/amd-nb] " tip-bot for Hans Rosenfeld
  -- strict thread matches above, loose matches on Subject: below --
2010-12-20 17:13 [PATCH 0/4] x86, amd: family 0x15 L3 cache features Hans Rosenfeld
2010-12-20 17:13 ` [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs Hans Rosenfeld

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