From: Andrew Lunn <andrew@lunn.ch>
To: Linus Walleij <linus.walleij@stericsson.com>
Cc: linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Grant Likely <grant.likely@secretlab.ca>,
Martin Persson <martin.persson@stericsson.com>,
Linus Walleij <linus.walleij@linaro.org>,
Lee Jones <lee.jones@linaro.org>
Subject: Re: [PATCH 0/4] Pinmux subsystem
Date: Tue, 3 May 2011 19:27:12 +0200 [thread overview]
Message-ID: <20110503172712.GE6538@lunn.ch> (raw)
In-Reply-To: <1304363768-30338-1-git-send-email-linus.walleij@stericsson.com>
On Mon, May 02, 2011 at 09:16:08PM +0200, Linus Walleij wrote:
> From: Linus Walleij <linus.walleij@linaro.org>
>
> This patchset creates a pinmux subsystem and switches U300 to use that new
> subsystem as an example. The problem is not that fantastically hard to
> solve in a general way, nobody got around to it because it requires some
> upfront code I believe, and this is my stab at it.
Hi Linus
I have some questions about how you see the following situations been
solved.
Say i have a UART core. I can be used as a 3-wire serial port, or
additionally it can have hardware flow control, or additionally it can
have all the modem signals. What would i expect to find in the pinmux
driver?
I can think of two different solutions:
1) Three functions: uart-3wire, uart-hw-flow, uart-hw-flow-modem. The
first just has 2 pins, the second 4 and the last 8. The board code
selects one of these for the serial driver to use.
2) Three functions: uart-core, uart-hw-flow, uart-mode. The first has
2 pins, the second has 2 pins and the last 4 pins. The board code tells
the driver to use uart-core, plus say uart-hw-flow.
Do you think the documentation should have guidelines how best to do
this sort of core + additional optional extras?
Say i have a SoC with an SPI core. This core has the usual MISC, MOSI
and SCLK. It additionally has 4 chip select lines. My board uses chip
select lines 2 and 3 for SPI, and select lines 0 and 1 as GPIO lines.
How does the pinmux driver handle this? Again, it is the problems of a
few core pins plus additional optional extras.
Maybe the documentation should make some recommendations about what is
placed into the drivers/pinmux/pinmux-foo.c and what should be kept in
the board specific code? Without these guidelines, it seems to me,
each board for a given SoC is going to add its own peculiar pin
combination to the drivers/pinmux/pinmux-foo.c file. Maybe it makes
more sense to have a collection of standard pin functions in
drivers/pinmux/pinmux-foo.c, which cover 75% of the likely
combinations. And recommend a board file to have its own additional
list of strange pin functions which it registers with the pinmux core?
Thanks
Andrew
next prev parent reply other threads:[~2011-05-03 17:48 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-05-02 19:16 Linus Walleij
2011-05-02 22:57 ` Russell King - ARM Linux
2011-05-10 21:25 ` Linus Walleij
2011-05-10 21:45 ` Russell King - ARM Linux
2011-05-10 23:15 ` Linus Walleij
2011-05-03 17:27 ` Andrew Lunn [this message]
2011-05-03 19:29 ` Valdis.Kletnieks
2011-05-10 21:42 ` Linus Walleij
2011-05-11 9:50 ` Andrew Lunn
2011-05-12 0:41 ` Linus Walleij
2011-05-12 7:00 ` Andrew Lunn
2011-05-15 13:33 ` Andrew Lunn
2011-05-15 17:50 ` Linus Walleij
2011-05-17 1:57 ` Kyungmin Park
2011-05-18 20:02 ` Linus Walleij
2011-05-18 21:21 ` Mark Brown
2011-05-12 7:44 ` Sascha Hauer
2011-05-12 9:40 ` Tony Lindgren
2011-05-12 14:02 ` Linus Walleij
2011-05-12 21:17 ` RE : " Matthieu Castet
2011-05-13 7:05 ` Linus Walleij
2011-05-13 16:03 ` Matthieu CASTET
2011-05-14 7:57 ` Linus Walleij
2011-05-13 9:59 ` Sascha Hauer
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