Re: [PATCH V2 1/4] perf: Add hardware breakpoint address mask

[Will Deacon <will.deacon@arm.com>]

On Tue, Apr 23, 2013 at 04:18:46PM +0100, Jacob Shin wrote:
> On Tue, Apr 23, 2013 at 04:02:40PM +0100, Will Deacon wrote:
> > On Tue, Apr 23, 2013 at 03:40:57PM +0100, Jacob Shin wrote:
> > > >   perf stat -e mem:0x1000/0xf:w a.out
> > 
> > Are you saying that this command would count any write to:
> > 
> > 	0x1000
> > 	0x1001
> > 	...
> > 	0x100e
> > 	0x100f
> > 
> > ?
> > 
> > If so, that differs from the ARM debug architecture in that the mask is called
> > `byte-address-select', so a mask of 0b1001 would count accesses at +0 bytes
> > and +3 bytes from the base address. Is that possible to describe with your
> > masking scheme and a single watchpoint?
> > 
> > A mask of 0xf, would count +0, +1, +2 and +3 (essentially bp_len == 4).
> > 
> > Unfortunately, that means I can't just invert the mask like I originally
> > thought.
> 
> Ah, .. that is different .
> 
> Our hardware matches on the breakpoint if:
> 
>   (physical_address & ~bp_addr_mask) == (bp_addr & ~bp_addr_mask)
> 
> In other words, the mask says which of the bp_addr bits hardware should
> ignore when matching.
> 
> .. it would be great if we can come up with userland interface that works
> for both archs. I'm coming up empty at the moment ..

After a bit of thought, I *think* the ARM mechanism is more expressive, and
you could describe your masking in terms of byte-address-select. The
downside is that we'd end up with much larger masks, which could be argued
as counter-intuitive from a user's point of view.

Will