[PATCH 1/3] spi: fix undefined behaviour in SPI_BPW_RANGE_MASK

[PATCH 1/3] spi: fix undefined behaviour in SPI_BPW_RANGE_MASK

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

The parameters to SPI_BPW_RANGE_MASK() are in the range 1..32. If 32 is
used as a parameter, part of the expression is "1 << 32". Since 32 is >=
the size of the type in use, such a shift is undefined behaviour. Add
macro SPI_BIT_MASK to Implement a special case and thus avoid undefined
behaviour. Use this new macro rather than BIT() when implementing
SPI_BPW_RANGE_MASK().

This fixes build warnings such as:
drivers/spi/spi-gpio.c:446:2: warning: left shift count >= width of type [enabled by default]

SPI_BPW_MASK() already avoids this, since its parameter is also in range
1..32, yet it only shifts by up to one less than the input parameter.

Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 include/linux/spi/spi.h |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 1737256..3e94791 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -309,7 +309,8 @@ struct spi_master {
 	/* bitmask of supported bits_per_word for transfers */
 	u32			bits_per_word_mask;
 #define SPI_BPW_MASK(bits) BIT((bits) - 1)
-#define SPI_BPW_RANGE_MASK(min, max) ((BIT(max) - 1) - (BIT(min) - 1))
+#define SPI_BIT_MASK(bits) (((bits) == 32) ? ~0UL : (BIT(bits) - 1))
+#define SPI_BPW_RANGE_MASK(min, max) (SPI_BIT_MASK(max) - SPI_BIT_MASK(min))
 
 	/* other constraints relevant to this driver */
 	u16			flags;
-- 
1.7.10.4

[PATCH 2/3] spi: fix incorrect handling of min param in SPI_BPW_RANGE_MASK

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

SPI_BPW_RANGE_MASK is intended to work by calculating two masks; one
representing support for all bits up-to-and-including the "max" supported
value, and one representing support for all bits up-to-but-not-including
the "min" supported value, and then taking the difference between the
two, resulting in a mask representing support for all bits between
(inclusive) the min and max values.

However, the second mask ended up representing all bits up-to-and-
including rather up-to-but-not-including. Fix this bug.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 include/linux/spi/spi.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 3e94791..28e440b 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -310,7 +310,7 @@ struct spi_master {
 	u32			bits_per_word_mask;
 #define SPI_BPW_MASK(bits) BIT((bits) - 1)
 #define SPI_BIT_MASK(bits) (((bits) == 32) ? ~0UL : (BIT(bits) - 1))
-#define SPI_BPW_RANGE_MASK(min, max) (SPI_BIT_MASK(max) - SPI_BIT_MASK(min))
+#define SPI_BPW_RANGE_MASK(min, max) (SPI_BIT_MASK(max) - SPI_BIT_MASK(min - 1))
 
 	/* other constraints relevant to this driver */
 	u16			flags;
-- 
1.7.10.4

[PATCH 3/3] spi: fix build break in spi-fsl-espi.c

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Fix a build error introduced by 24778be "spi: convert drivers to use
bits_per_word_mask":

drivers/spi/spi-fsl-espi.c:162:13: error: expected '=', ',', ';', 'asm' or '__attribute__' before '->' token

Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 drivers/spi/spi-fsl-espi.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c
index 0ef05f1..6a74d78 100644
--- a/drivers/spi/spi-fsl-espi.c
+++ b/drivers/spi/spi-fsl-espi.c
@@ -153,7 +153,7 @@ static int fsl_espi_setup_transfer(struct spi_device *spi,
 	cs->get_tx = mpc8xxx_spi_tx_buf_u32;
 	if (bits_per_word <= 8) {
 		cs->rx_shift = 8 - bits_per_word;
-	} else
+	} else {
 		cs->rx_shift = 16 - bits_per_word;
 		if (spi->mode & SPI_LSB_FIRST)
 			cs->get_tx = fsl_espi_tx_buf_lsb;
-- 
1.7.10.4

Re: [PATCH 1/3] spi: fix undefined behaviour in SPI_BPW_RANGE_MASK

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 362 bytes --]

On Thu, May 30, 2013 at 09:59:39AM -0600, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> The parameters to SPI_BPW_RANGE_MASK() are in the range 1..32. If 32 is
> used as a parameter, part of the expression is "1 << 32". Since 32 is >=
> the size of the type in use, such a shift is undefined behaviour. Add

Applied all, thanks.

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]